AD9857/PCB Analog Devices Inc, AD9857/PCB Datasheet
AD9857/PCB
Specifications of AD9857/PCB
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AD9857/PCB Summary of contents
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FEATURES 200 MHz internal clock rate 14-bit data path Excellent dynamic performance SFDR @ 65 MHz (±100 kHz) A OUT 4× to 20× programmable reference clock multiplier Reference clock multiplier PLL lock detect indicator Internal 32-bit quadrature DDS ...
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AD9857 TABLE OF CONTENTS Revision History ............................................................................... 3 General Description ......................................................................... 4 Specifications..................................................................................... 5 Absolute Maximum Ratings............................................................ 8 Explanation of Test Levels........................................................... 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Typical Performance Characteristics ........................................... 11 Modulated Output Spectral ...
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REVISION HISTORY 5/04−Data Sheet Changed from Rev Rev. C Changes to 14-Bit D/A Converter Section ..................................22 Changes to Register Address 0Ch, Bit 1 Equation ......................28 Changes to Register Address 12h, Bit 1 Equation .......................28 Changes to Register Address ...
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AD9857 GENERAL DESCRIPTION The AD9857 integrates a high speed direct digital synthesizer (DDS), a high performance, high speed, 14-bit digital-to-analog converter (DAC), clock multiplier circuitry, digital filters, and other DSP functions onto a single chip, to form a complete quadrature ...
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SPECIFICATIONS V = 3.3 V ± 5 1.96 kΩ, external reference clock frequency = 10 MHz with REFCLK multiplier enabled at 20×. S SET Table 1. Parameter REF CLOCK INPUT CHARACTERISTICS Frequency Range REFCLK Multiplier Disabled REFCLK Multiplier ...
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AD9857 Parameter MODULATOR CHARACTERISTICS (65 MHz A (Input data: 2.5 MS/s, QPSK, 4× oversampled, inverse SINC filter ON, inverse CIC ON) I/Q Offset Error Vector Magnitude INVERSE SINC FILTER (variation in gain from MHz, inverse SINC filter ...
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Parameter 3 POWER SUPPLY V CURRENT (all power specifications 3.3 V, 25°C, REFCLK = 200 MHz) DD Full Operating Conditions 160 MHz Clock (×16) 120 MHz Clock (×12) Burst Operation (25%) Single-Tone Mode Power-Down Mode Full-Sleep ...
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AD9857 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS D13 D12 D11 D10 DVDD DVDD DVDD DGND DGND DGND CONNECT Table 4. Pin Function Descriptions Pin Number Mnemonic I/O Function 20–14, 7–1 D0–D6, D7– I 14-Bit Parallel Data Bus for I ...
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AD9857 Pin Number Mnemonic I/O Function 35, 37, 38, 43, AVDD 3.3 V Analog Power pin(s). 48, 54, 58, 64 36, 39, 40, 42, AGND Analog Ground pin(s). 44, 47, 53, 56, 59, 61 IOUT O DAC Output ...
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TYPICAL PERFORMANCE CHARACTERISTICS MODULATED OUTPUT SPECTRAL PLOTS 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 START 0Hz 5MHz/ Figure 3. QPSK at 42 MHz and 2.56 MS/s; 10.24 MHz External Clock with REFCLK Multiplier = 12, CIC ...
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AD9857 SINGLE-TONE OUTPUT SPECTRAL PLOTS 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 START 0Hz 10MHz/ Figure 7. 21 MHz Single-Tone Output 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 START 0Hz 10MHz/ Figure ...
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NARROW-BAND SFDR SPECTRAL PLOTS 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 10kHz/ CENTER 70.1MHz Figure 11. 70.1 MHz Narrow-Band SFDR, 10 MHz External Clock with REFCLK Multiplier = 20 0 –10 –20 –30 –40 –50 –60 ...
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AD9857 OUTPUT CONSTELLATIONS 1 CONST 200m/DIV –1 –1.3071895838 Figure 13. QPSK, 65 MHz, 2.56 MS/s 1 CONST 200m/DIV –1 –1.3071895838 Figure 14. 64-QAM, 42 MHz, 6 MS/s 1 CONST 200m/DIV –1 –1.3071895838 Figure 15. GMSK Modulation, 13 MS/s 1 CONST ...
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MODES OF OPERATION The AD9857 has three operating modes: • Quadrature modulation mode (default) • Single-tone mode • Interpolating DAC mode Mode selection is accomplished by programming a control register via the serial port. The inverse SINC filter and output ...
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AD9857 SINGLE-TONE MODE A block diagram of the AD9857 operating in the single-tone mode is shown in Figure 19. In the single-tone mode, both the I and Q data paths are disabled from the 14-bit parallel data port up to ...
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INTERPOLATING DAC MODE A block diagram of the AD9857 operating in the interpolating DAC mode is shown in Figure 20. In this mode, the DDS and modulator are both disabled and only the I data path is active. The Q ...
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AD9857 SIGNAL PROCESSING PATH To better understand the operation of the AD9857 it is helpful to follow the signal path from input, through the device, to the output, examining the function of each block (refer to Figure 1). The input ...
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TxENABLE t DS PDCLK D<13:0> Figure 21. 14-Bit Parallel Port Timing Diagram—Quadrature Modulation Mode TxENABLE t DS PDCLK D<13:0> Figure 22. 14-Bit Parallel Port Timing Diagram—Interpolating DAC Mode ...
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AD9857 Fixed Interpolator (4×) This block is a fixed 4× interpolator implemented as two half-band filters. The output of this stage is the original data upsampled by 4×. Before presenting a detailed description of the half-band filters, recall ...
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A) BANDWIDTH DATA 1 SAMPLE RATE f f (@1 ) NYQ 0 DATA VECTOR RATE = INPUT TO AD9857 2× OVERSAMPLE RATE f f (@1 ) ...
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AD9857 The equation relating output frequency (f digital modulator to the frequency tuning word (FTWORD) and the system clock (SYSCLK × FTWORD SYSCLK 2 / OUT where f and SYSCLK frequencies are in Hz ...
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The output compliance voltage of the AD9857 is −0 +1.0 V. Any signal developed at the DAC output should not exceed 1.0 V, otherwise, signal distortion results. Furthermore, the signal may extend below ground as much as 0.5 ...
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AD9857 INPUT DATA PROGRAMMING CONTROL INTERFACE—SERIAL I/O The AD9857 serial port is a flexible, synchronous, serial communications port allowing easy interface to many industry- standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both ...
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CS SCLK SDIO 1ST BIT SDO SYMBOL DEFINITION t DATA VALID TIME DV Figure 28. Timing Diagram for Data Read from AD9857 INSTRUCTION CYCLE CS SCLK SDIO Figure ...
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AD9857 INSTRUCTION BYTE The instruction byte contains the information shown in Table 6. Table 6. Instruction Byte Information MSB R Bit 7 of the instruction byte determines whether a read ...
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When synchronization is lost between the system and the AD9857, the SYNC I/O pin provides a means to re-establish synchronization without reinitializing the entire chip. The SYNC I/O pin enables the user to reset the AD9857 state machine to accept ...
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AD9857 PROFILE #1 Tuning Word—Register Address 08h, Bits The lower byte of the 32-bit frequency tuning word, Bits 0–7. Tuning Word—Register Address 09h, Bits ...
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Table 8. Control Register Quick Reference Register (MSB) Address Bit 7 Bit 6 00h SDIO Input Only LSB First 01h CIC Clear Inverse SINC Bypass 02h 03h 04h 05h 06h CIC Interpolation Rate 01h: Bypass CIC Filter 02h–3Fh: Interpolation Factor ...
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AD9857 LATENCY The latency through the AD9857 is easiest to describe in terms of system clock (SYSCLK) cycles. Latency is a function of the AD9857 configuration (that is, which mode and which optional features are engaged). The latency is primarily ...
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SYSCLK/N SYSCLK/2N SYSCLK/4N PDCLK TxENABLE D<13:0> DON'T CARE SIGNAL PATH I SIGNAL PATH Q INVCIC CLOCK Figure 33. Latency from D<13:0> to Signal Processing Chain, Four PDCLK Cycles SYSCLK/N SYSCLK/2N SYSCLK/4N PDCLK TxENABLE I DON'T CARE 0 D<13:0> SIGNAL PATH ...
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AD9857 EASE OF USE FEATURES PROFILE SELECT The profile select pins, PS0 and PS1, activate one of four internal profiles within the device. A profile is defined as a group of control registers. The AD9857 contains four identical register groupings ...
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If the user requires the PDCLK to continue running, the PLL lock control bit (Control Register 00h<5>) can be set to a Logic 1. When the PLL lock control bit is set, the PLL lock indicator pin functionality remains the ...
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AD9857 HARDWARE-CONTROLLED DIGITAL POWER-DOWN The hardware-controlled method for reducing power is to apply a Logic 1 to the DPD pin. Restarting the part after a digital power-down is accomplished by applying a Logic 0 to the DPD pin. The DPD ...
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... Equivalent I/O Circuits IOUT IOUTB DAC OUTPUTS Figure 35. Equivalent I/O Circuits SUPPORT Applications assistance is available for the AD9857 and the AD9857/PCB evaluation board. Please call 1-800-ANALOGD or visit www.analog.com/dds. Rev. C| Page AD9857 V DD DIGITAL DIGITAL OUT IN ...
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AD9857 A. Top View B. Ground Plane C. Power Plane D. Bottom View Figure 36. Application–Example Circuits Rev Page ...
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W8 W10 W9 W7 GND DVDD AVDD GND VCC TB1 POWER CONNECTION PARALLEL PORT U1 VCC 74HC574 OUT_EN VCC ...
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AD9857 OUTLINE DIMENSIONS 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW 0.75 1.60 0.60 MAX 0. SEATING PLANE 10° 6° 0.20 2° 0.09 VIEW A 7° 20 3.5° 21 0° 0.10 MAX COPLANARITY COMPLIANT ...
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... ORDERING GUIDE Model Temperature Range AD9857AST −40°C to +85°C 1 AD9857ASTZ −40°C to +85°C AD9857/PCB Pb-free part. Package Description LQFP LQFP Evaluation Board Rev. C| Page AD9857 Package Option ST-80 ST-80 ...
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AD9857 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01018–0–5/04(C) Rev Page ...