AD9954YSV Analog Devices Inc, AD9954YSV Datasheet
AD9954YSV
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AD9954YSV Summary of contents
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FEATURES 400 MSPS internal clock speed Integrated 14-bit DAC Programmable phase/amplitude dithering 32-bit frequency tuning accuracy 14-bit phase tuning accuracy Phase noise better than –120 dBc/Hz Excellent dynamic performance >80 dB narrowband SFDR Serial I/O control Ultrahigh speed analog comparator ...
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AD9954 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Basic Block Diagram ........................................................................ 1 Revision History ............................................................................... 2 Functional Block Diagram .............................................................. 3 Electrical Specifications ................................................................... 4 Absolute Maximum Ratings ............................................................ 7 Explanation of Test ...
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FUNCTIONAL BLOCK DIAGRAM FREQUENCY ACCUMULATOR 32 STATIC RAM 1024 × I/O UPDATE 0 M SYNC_CLK U X OSCILLATOR/BUFFER REFCLK REFCLK ENABLE CRYSTAL OUT DDS CORE PHASE M ACCUMULATOR U RAM PHASE X DATA OFFSET –1 Z ...
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AD9954 ELECTRICAL SPECIFICATIONS Unless otherwise noted, AVDD, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, R 400 MHz. DAC output must be referenced to AVDD, not AGND. Table 1. Parameter REF CLOCK INPUT CHARACTERISTICS Frequency Range ...
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Parameter COMPARATOR INPUT CHARACTERISTICS Input Capacitance Input Resistance Input Current Hysteresis COMPARATOR OUTPUT CHARACTERISTICS Logic 1 Voltage, High-Z Load Logic 0 Voltage, High-Z Load Propagation Delay Output Duty-Cycle Error Rise/Fall Time Load Toggle Rate, High-Z Load 1 Output ...
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AD9954 Parameter CMOS LOGIC INPUTS Logic 1 Voltage @ DVDD_I/O (Pin 43) = 1.8 V Logic 0 Voltage @ DVDD_I/O (Pin 43) = 1.8 V Logic 1 Voltage @ DVDD_I/O (Pin 43) = 3.3 V Logic 0 Voltage @ DVDD_I/O ...
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ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Maximum Junction Temperature DVDD_I/O (Pin 43) AVDD, DVDD Digital Input Voltage (DVDD_I/O = 3.3 V) Digital Input Voltage (DVDD_I/O = 1.8 V) Digital Output Current Storage Temperature Range Operating Temperature Range Lead Temperature (10 ...
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AD9954 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CRYSTAL OUT CLKMODESELECT Note that the exposed paddle on the bottom of the package forms an electrical connection for the DAC and must be attached to analog ground. Note that Pin 43, DVDD_I/O, can ...
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Pin No. Mnemonic I/O 31 COMP_IN I 35 PWRDWNCTL I 36 RESET I 37 IOSYNC I 38 SDO SCLK I 41 SDIO I/O 43 DVDD_I SYNC_IN I 45 SYNC_CLK O 46 OSK I ...
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AD9954 TYPICAL PERFORMANCE CHARACTERISTICS REF 0dBm ATTEN 10dB 0 PEAK LOG 1R 10dB/ –10 –20 –30 –40 MARKER 101MHz –70.68dB –50 – – –80 –90 –100 CENTER 100MHz #RES BW 3kHz VBW 3kHz Figure ...
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REF –4dBm ATTEN 10dB 1 0 PEAK LOG 10dB/ –10 –20 –30 –40 MARKER 1.105000MHz –5.679dBm –50 – –70 AA –80 –90 ST –100 CENTER 1.105MHz #RES BW 30Hz VBW 30Hz SWEEP 199.2 s (401 PTS) ...
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AD9954 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 10 100 1k 10k f (Hz) Figure 17. Residual Phase Noise with 400 MSPS; PLL Bypassed (Green), PLL ...
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THEORY OF OPERATION COMPONENT BLOCKS REFCLK Input The AD9954 supports several methods for generating the internal system clock. An on-chip oscillator circuit is available for initiating the low frequency reference signal by connecting a crystal to the clock input pins. ...
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AD9954 Comparator Some applications (for example, clocking) prefer a square-wave signal rather than a sine wave. In support of such applications, the AD9954 includes an on-chip comparator. The comparator has a bandwidth greater than 200 MHz and a common-mode input ...
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Clear-and-Release Function When set for auto clearing, the corresponding accumulator is cleared and then begins to accumulate again upon receipt of an I/O update or change on one of the profile pins. This is repeated for every subsequent I/O update ...
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AD9954 Manual Shaped On-Off Keying Mode Operation When configured for manual shaped on-off keying, the content of the ASFR sets the scale factor for the data path. MODES OF OPERATION Single-Tone Mode In single-tone mode, the DDS core uses a ...
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Upon entering this mode (via an I/O update or changing the PS0 pin), the RAM address generator loads the RAM segment beginning address bits of RSCW0 and the ramp rate timer loads the RAM segment address ramp rate bits. The ...
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AD9954 Table 8. Internal Profile Control CFR1<29:27> (Binary) Mode Description 000 Internal control inactive 001 Internal control active, single-burst, activate Profile 0, then Profile 1, then stop 010 Internal control active, single-burst, activate Profile 0, then Profile 1, then Profile ...
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OUT FTW1 FTW0 SINGLE-TONE MODE PS<0> POINT A: LOAD RISING RAMP RATE REGISTER, APPLY RISING DFTW. AT POINT B: LOAD FALLING RAMP RATE REGISTER, APPLY FALLING DFTW. f OUT FTW1 FTW0 SINGLE-TONE MODE PS<0> ...
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AD9954 The last method in which the sweep ramp rate timer can be reset is changing from inactive linear sweep mode to active linear sweep mode using the linear sweep enable bit (CFR1<21>). For methods two and three, the ramp ...
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SYNCHRONIZATION—REGISTER UPDATES (I/O UPDATE) Functionality of the SYNC_CLK and I/O UPDATE Data into the AD9954 is synchronous to the SYNC_CLK signal (supplied externally to the user on the SYNC_CLK pin). The I/O UPDATE pin is sampled on the rising edge ...
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AD9954 Synchronizing Multiple AD9954s There are three modes of synchronization available to the user: an automatic synchronization mode, a software-controlled manual synchronization mode, and a hardware-controlled manual synchronization mode. The following requirements apply to all modes. First, all units must ...
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Serial I/O Port The AD9954 serial port is a flexible, synchronous, serial communications port that easily interfaces to many industry- standard microcontrollers and microprocessors. The serial I/O port is compatible with most synchronous transfer formats, including both the Motorola 6905/11 ...
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AD9954 CS SCLK I SDIO 7 SERIAL INTERFACE PORT PIN DESCRIPTIONS SCLK—Serial Clock. The serial clock pin is used to synchronize data to and from the AD9954 and to run internal state machines. SCLK maximum frequency is 25 MHz. CS ...
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When in LSB first mode, the first data byte is for the least significant byte of the memory (specified by the beginning address) with the ...
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AD9954 Table 12. Register Map—When Linear Sweep Enable Bit Is False (CFR1<21> Note that the RAM Enable Bit CFR1<31> only activates the RAM itself, not the RAM segment control words. Register Name (Serial Bit (MSB) Address) Range Bit ...
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Register Name (Serial Bit (MSB) Address) Range Bit 7 Profile 1 <7:0> RAM Segment 1 Mode Control<2:0> RAM Segment <15:8> Control Word No. 1 <23:16> (RSCW1) (0x08) <31:24> <39:32> Profile 2 <7:0> RAM Segment 2 Mode Control<2:0> RAM Segment <15:8> ...
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AD9954 Table 13. Register Map—When Linear Sweep Enable Bit Is True (CFR1<21> Note that the RAM Enable Bit CFR1<31> only activates the RAM itself, not the RAM segment control words. Register Name Bit (MSB) (Serial Address) Range Bit ...
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CONTROL REGISTER BIT DESCRIPTIONS Control Function Register No. 1 (CFR1) The CFR1 is used to control the various functions, features, and modes of the AD9954. The functionality of each bit follows. CFR1<31>: RAM Enable Bit CFR1<31> (default). The ...
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AD9954 CFR1<10>: Clear Phase Accumulator CFR1<10> (default). The phase accumulator functions as normal. CFR1<10> The phase accumulator memory elements are cleared and held clear until this bit is cleared. CFR1<9>: SDIO Input Only CFR1<9> ...
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CFR2<2>: VCO Range Control Bit CFR2<2> (default), VCO operates between 100 MHz and 250 MHz. CFR2<2> VCO operates between 250 MHz and 400 MHz. CFR2<1:0>: Charge Pump Current Control Bits These bits are used to control ...
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AD9954 LAYOUT CONSIDERATIONS For the best performance, the following layout guidelines should be observed. Always separate the analog power supply (AVDD) and the digital power supply (DVDD), even if just from two different voltage regulators driven by a common supply. ...
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DETAILED PROGRAMMING EXAMPLES SINGLE-TONE MODE In this example, the part is programmed to output a 122 MHz single-tone carrier, the device is clocked with a 20 MHz crystal oscillator, and the clock multiplier is used to push the internal system ...
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AD9954 Because there is a ramp-up, but no ramp-down, RAM mode, two RAM segments are generated; one for the transition from F0 to F1, and one for the transition from F1 to F0. Step through the intermediary frequencies as quickly ...
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SUGGESTED APPLICATION CIRCUITS RF/IF INPUT AD9954 LPF REFCLK Figure 31. Synchronized LO for Upconversion/Downconversion PHASE LOOP COMPARATOR FILTER REF SIGNAL AD9954 FILTER TUNING WORD Figure 32. Digitally Programmable Divide-by-N Function in PLL TUNING WORD IOUT AD9954 DDS IOUT AD9954 ON-CHIP ...
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AD9954 EVALUATION BOARD SCHEMATICS I/O_SYNC_DUT1 IOSYNC 37 SDO SDO 38 CSB_DUT1 CS 39 SCLK SCLK 40 SDIO SDIO 41 GND DGND 42 DVDD_I/O DVDD_I/O 43 SYNCMULTI_DUT1 SYNC_IN 44 SYNCMULTI_DUT2 SYNC_CLK 45 OSK_DUT1 OSK 46 PS0_DUT1 PS0 47 PS1_DUT1 PS1 48 ...
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I/O_SYNC_DUT2 IOSYNC 37 SDO SDO 38 CSB_DUT2 CS 39 SCLK SCLK 40 SDIO SDIO 41 GND DGND 42 DVDD_I/O DVDD_I/O 43 SYNCMULTI_DUT2 SYNC_IN 44 SYNCMULTI_DUT1 SYNC_CLK 45 OSK_DUT2 OSK 46 PS0_DUT2 PS0 47 PS1_DUT2 PS1 48 SET DAC_R 24 DACBP ...
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AD9954 Figure 37. Evaluation Board Interface Logic Rev Page 03374-035 ...
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... COPLANARITY VIEW A ROTATED 90 ° CCW ORDERING GUIDE Temperature Model Range AD9954YSV −40°C to +105°C AD9954YSV-REEL7 −40°C to +105°C 1 AD9954YSVZ −40°C to +105°C AD9954YSVZ-REEL7 1 −40°C to +105°C 1 AD9954/PCBZ RoHS Compliant Part. 1.20 9.00 MAX BSC SQ BOTTOM VIEW 48 37 ...
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AD9954 NOTES ©2003–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03374-0-5/09(B) Rev Page ...