AD9854ASQ Analog Devices Inc, AD9854ASQ Datasheet
AD9854ASQ
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AD9854ASQ Summary of contents
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FEATURES 300 MHz internal clock rate FSK, BPSK, PSK, chirp, AM operation Dual integrated 12-bit digital-to-analog converters (DACs) Ultrahigh speed comparator rms jitter Excellent dynamic performance 80 dB SFDR at 100 MHz (±1 MHz) A OUT 4× to ...
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AD9854 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Specifications..................................................................................... 5 Absolute Maximum Ratings............................................................ 8 Explanation of Test Levels ........................................................... 8 ESD Caution.................................................................................. 8 Pin Configuration and ...
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REVISION HISTORY 11/06—Rev Rev. D Changes to General Description Section .......................................4 Changes to Endnotes in the Power Supply Parameter .................7 Changes to Absolute Maximum Ratings Section..........................8 Added Endnotes to Table 2 ..............................................................8 Changes to Figure 50 ......................................................................29 Changes ...
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AD9854 GENERAL DESCRIPTION The AD9854 digital synthesizer is a highly integrated device that uses advanced DDS technology, coupled with two internal high speed, high performance quadrature DACs to form a digitally programmable I and Q synthesizer function. When referenced to ...
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... SPECIFICATIONS V = 3.3 V ± 5 3.9 kΩ, external reference clock frequency = 30 MHz with REFCLK multiplier enabled at 10× for AD9854ASQ, S SET external reference clock frequency = 20 MHz with REFCLK multiplier enabled at 10× for AD9854AST, unless otherwise noted. Table 1. Parameter REFERENCE CLOCK INPUT CHARACTERISTICS ...
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... MHz (±250 MHz) 41 MHz (±50 MHz) 119 MHz (±1 MHz) 119 MHz (±250 MHz) 119 MHz (±50 MHz) 9 CLOCK GENERATOR OUTPUT JITTER 5 MHz A OUT 40 MHz A OUT 100 MHz A OUT AD9854ASQ Test Level Temp Min Typ Max 25°C V 140 25°C V 138 25°C ...
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... All functions except inverse sinc engaged. 14 All functions except inverse sinc and digital multipliers engaged most cases, disabling the inverse sinc filter can resolve exceeding the maximum die temperature. The inverse sinc filter consumes approximately 30% of the total power. AD9854ASQ Test Level Temp Min Typ ...
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AD9854 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Maximum Junction Temperature V S Digital Inputs Digital Output Current Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Maximum Clock Frequency (ASQ) Maximum Clock Frequency (AST θ (ASQ) ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DVDD DVDD DGND DGND NC A2/IO RESET A1/SDO A0/SDIO I/O UD CLK CONNECT Table 3. Pin Function Descriptions Pin No. Mnemonic 10, 23, 24, 25, ...
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AD9854 Pin No. Mnemonic 20 I/O UD CLK 21 WR/SCLK 22 RD/CS 29 FSK/BPSK/HOLD 30 OSK AVDD 31, 32, 37, 38, 44, 50, 54, 60, 65 33, 34, 39, 40, 41, AGND 45, 46, 47, 53, 59, 62, 66, 67 ...
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AVDD AVDD I I OUT OUTB MUST TERMINATE OUTPUTS FOR CURRENT FLOW. DO NOT EXCEED THE OUTPUT VOLTAGE COMPLIANCE RATING. A. DAC OUTPUTS B. COMPARATOR OUTPUT AVDD VINP/ VINN COMPARATOR OUT C. COMPARATOR INPUT Figure 3. Equivalent Input and Output ...
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AD9854 TYPICAL PERFORMANCE CHARACTERISTICS Figure 4 to Figure 9 indicate the wideband harmonic distortion performance of the AD9854 from 19.1 MHz to 119.1 MHz fundamental output, reference clock = 30 MHz, REFCLK multiplier = 10. Each graph plotted from 0 ...
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Figure 10 to Figure 15 show the trade-off in elevated noise floor, increased phase noise, and discrete spurious energy when the internal REFCLK multiplier circuit is engaged. Plots with wide (1 MHz) and narrow (50 kHz) spans are shown. Compare ...
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AD9854 Figure 16 and Figure 17 show the narrow-band performance of the AD9854 when operating with a 20 MHz reference clock and the REFCLK multiplier enabled at 10× vs. a 200 MHz reference clock with the REFCLK multiplier bypassed. 0 ...
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RISE TIME 1.04ns –33ps 0ps 500ps/DIV 232mV/DIV 50 Ω INPUT Figure 22. Typical Comparator Output Jitter, 40 MHz A with REFCLK Multiplier Bypassed CH1 500mVΩ M 500ps CH1 Figure 23. Comparator Rise/Fall Times 1200 1000 800 600 JITTER [10.6ps RMS] ...
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AD9854 TYPICAL APPLICATIONS RF/IF INPUT I BASEBAND Q BASEBAND VCA FUNDAMENTAL LPF COS LPF CHANNEL AD9854 SELECT FILTERS LPF REFCLK SIN LPF Figure 25. Quadrature Downconversion COS LPF AD9854 LPF REFCLK SIN Figure 26. Direct Conversion Quadrature ...
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REFERENCE CLOCK PHASE LOOP COMPARATOR FILTER FILTER REF CLK IN AD9854 DAC OUT DDS PROGRAMMABLE DIVIDE-BY-N FUNCTION (WHERE TUNING WORD Figure 29. Programmable Fractional Divide-by-N Synthesizer REF CLOCK AD9854 FILTER PHASE DDS COMPARATOR TUNING DIVIDE-BY-N WORD Figure ...
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AD9854 REFERENCE CLOCK AD9854 8-BIT PARALLEL OR µPROCESSOR/ SERIAL PROGRAMMING CONTROLLER DATA AND CONTROL FPGA, ETC. SIGNALS 300MHz MAX DIRECT MODE OR 15MHz TO 75MHz REFERENCE MAX IN THE 4× TO 20× CLOCK CLOCK MULTIPLIER MODE 2kΩ R SET Figure ...
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THEORY OF OPERATION The AD9854 quadrature output digital synthesizer is a highly flexible device that addresses a wide range of applications. The device consists of an NCO with a 48-bit phase accumulator, a programmable reference clock multiplier, inverse sinc filters, ...
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AD9854 F1 MODE 000 (DEFAULT) TW1 MASTER RESET I/O UD CLK As with all Analog Devices DDS devices, the value of the frequency tuning word is determined by FTW = (Desired Output Frequency × 2 where the phase ...
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MODE 000 (DEFAULT) TW1 0 TW2 0 I/O UD CLK FSK DATA (PIN 29) Figure 36. Traditional FSK Mode MODE 000 (DEFAULT) TW1 0 TW2 0 DFW I/O UD CLK FSK DATA (PIN 29) ...
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AD9854 Frequency ramping, whether linear or nonlinear, necessitates that many intermediate frequencies between F1 and F2 are output in addition to the primary F1 and F2 frequencies. Figure 37 and Figure 38 depict the frequency vs. time characteristics of a ...
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MODE FSK DATA TRIANGLE I/O UD CLK MODE 000 (DEFAULT) TW1 0 TW2 0 I/O UD CLK FSK DATA Figure 41 shows that premature toggling causes the ramp to immediately reverse itself and proceed at the same ...
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AD9854 Nonlinear ramped FSK has the appearance of a chirp function, as Figure 43 shows. The difference between a ramped FSK function and a chirp function is that FSK is limited to operation between F1 and F2. Chirp operation has ...
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The AD9854 permits precise, internally generated linear, or externally programmed nonlinear, pulsed or continuous FM over the complete frequency range, duration, frequency resolution, and sweep direction(s). All of these are user programmable. Figure 44 shows a block diagram of the ...
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AD9854 F1 0 000 (DEFAULT) MODE 0 FTW1 DFW RAMP RATE I/O UD CLK CLR ACC1 F1 0 MODE 000 (DEFAULT) TW1 0 DPW RAMP RATE CLR ACC2 I/O UD CLK F1 0 000 (DEFAULT) MODE TW1 0 DFW RAMP ...
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MODE FTW1 PHASE ADJUST 1 PHASE ADJUST 2 BPSK DATA I/O UD CLK The 32-bit automatic I/O update counter can be used to construct complex chirp or ramped FSK sequences. Because this internal counter is synchronized ...
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AD9854 USING THE AD9854 INTERNAL AND EXTERNAL UPDATE CLOCK This update clock function is comprised of a bidirectional I/O pin, Pin 20, and a programmable 32-bit down-counter. To program changes that are to be transferred from the I/O buffer registers ...
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DIGITAL SIGNAL IN DDS DIGITAL OUTPUT USER-PROGRAMMABLE Figure 50. Block Diagram of Q DAC Pathway of the Digital Multiplier Section Responsible for the Shaped Keying Function The two fixed elements of the transition time are the period of the system ...
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AD9854 appreciable amplitude variations as a function of frequency. The inverse sinc function can be bypassed to reduce power consumption significantly, especially at higher clock speeds. When the Q DAC is configured as a control DAC, the inverse sinc function ...
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PROGRAMMING THE AD9854 The AD9854 register layout, shown in Table 7, contains the information that programs the chip for the desired functionality. While many applications require very little programming to configure the AD9854, some make use of all 12 accessible ...
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AD9854 Table 7. Register Layout Parallel Serial Address Address (Hex) (Hex) Bit 7 Bit Phase Adjust Register 1 <13:8> (Bits 15, 14, don’t care) 01 Phase Adjust Register 1 <7:0> Phase Adjust Register 2 <13:8> ...
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PARALLEL I/O OPERATION With the S/P SELECT pin tied high, the parallel I/O mode is active. The I/O port is compatible with industry-standard DSPs and microcontrollers. Six address bits, eight bidirectional data bits, and separate write/read control inputs make up ...
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AD9854 A<5:0> A1 D<7:0> RDHOZ t AHD SPECIFICATION t ADV t AHD t RDLOV t RDHOZ A<5:0> A1 D<7:0> WRHIGH SPECIFICATION t ASU t DSU t ADH t DHD t WRLOW t WRHIGH t ...
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GENERAL OPERATION OF THE SERIAL INTERFACE There are two phases to a serial communication cycle with the AD9854. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9854, coincident with the first eight ...
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AD9854 INSTRUCTION BYTE The instruction byte contains the following information. Table 10. Instruction Byte Information MSB R —Bit 7 determines whether a read or write data transfer occurs following the ...
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MSB/LSB TRANSFERS The AD9854 serial port can support MSB-first and LSB-first data formats. This functionality is controlled by Bit 1 of Serial Register Bank 20 hex. When this bit is set active high, the AD9854 serial port is in LSB-first ...
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AD9854 INSTRUCTION CYCLE CS SCLK SDIO INSTRUCTION CYCLE CS SCLK SDIO SDO INSTRUCTION CYCLE CS SCLK SDIO INSTRUCTION CYCLE CS SCLK I ...
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... PCB. In addition, the thermally enhanced package of the AD9854ASQ contains a heat sink on the bottom of the package that must be soldered to a ground pad on the PCB surface. This pad must be connected to a large copper plane, which, for convenience, can be a ground plane ...
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... The first step in applying the AD9854 is to select the internal clock frequency. Clock frequency selections above 200 MHz require the use of the thermally enhanced package (AD9854ASQ); other clock frequencies may allow the use of the standard plastic surface-mount package, but more information is needed to make that determination ...
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... THERMALLY ENHANCED PACKAGE MOUNTING GUIDELINES This section provides general recommendations for mounting the AD9854ASQ (the thermally enhanced exposed heat sink package) to printed circuit boards. The exceptional thermal characteristics of this package depend entirely on proper mechanical attachment. Figure 64 shows the package from the bottom and the dimen- sions of the exposed heat sink ...
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... PCB reference design. EVALUATION BOARD INSTRUCTIONS The AD9852/AD9854 Revision E evaluation board includes either an AD9852ASQ or AD9854ASQ IC. The ASQ package permits 300 MHz operation by virtue of its thermally enhanced design. This package has a bottom-side heat slug that must be soldered to the ground plane of the PCB directly beneath the IC ...
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W7 and W10 should be removed and 50 Ω test signals applied at J4 and J5 inputs to the 50 Ω elliptic filters. Users should refer to the schematic provided and to the following sections to properly position ...
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AD9854 and W8 3-pin header switches. The configuration described in the Observing the Filtered IOUT1 and the Filtered IOUT2 section must be used. Follow Steps 1 through 4 in that section, and then install shorting jumpers on Pin 1 and ...
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PLLFLT GND3 NC5 DIFFCLKEN AVDD CLKVDD CLKGND GND4 CLK8 REFCLK CLK REFCLK PMODE SPSELECT RESET MRESET OPTGND DVDD6 DVDD DVDD7 DGND6 DGND7 DGND8 DGND9 DVDD DVDD8 DVDD9 COUTGND2 GND COUTGND GND COUTVDD2 AVDD COUTVDD AVDD VOUT NC2 DACDGND2 GND DACDGND ...
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AD9854 Figure 69. Evaluation Board Schematic Rev Page 00636-069 ...
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Figure 70. Assembly Drawing Figure 71. Top Routing Layer, Layer 1 Rev Page AD9854 ...
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AD9854 Figure 72. Power Plane Layer, Layer 3 Figure 73. Ground Plane Layer, Layer 2 Rev Page ...
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... Table 12. AD9852/AD9854 Customer Evaluation Board (AD9852 PCB > AD9852ASQ; AD9854 PCB > AD9854ASQ) No. Quantity REFDES 1 3 C1, C2, C45 C14, C16 to C20, C22 to C24, C26 to C29, C44 3 2 C4, C37 4 2 C5, C38 5 3 C6, C21, C25 6 2 C30, C39 7 2 C31, C40 8 2 C32, C41 9 2 C33, C42 ...
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... Rubber bumper Square black 0 Ω jumper 1206 Pin socket XTAL COSC Rev Page Value Mfg. Part No. Wieland 25.602.2453.0 block Z5.530.3425.0 pins AD9852ASQ or AD9854ASQ SN74HC125D MC100LVEL16D SN74HC14D SN74HC574DW AMP 552742-1 SAMTEC SAMTEC 3M SJ-5018SPBL GSO2669 Rev Ω AMP 5-330808-6 (Not supplied) ...
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... PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range 1 AD9854ASQ −40°C to +85° AD9854ASQZ −40°C to +85°C AD9854AST −40°C to +85°C 2 AD9854ASTZ −40°C to +85°C AD9854/PCB 1 Contact an Analog Devices sales representative for availability Pb-free part. ...
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AD9854 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00636-0-11/06(D) Rev Page ...