PPC405EP-3LB333C Applied Micro Circuits Corporation, PPC405EP-3LB333C Datasheet - Page 37

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PPC405EP-3LB333C

Manufacturer Part Number
PPC405EP-3LB333C
Description
Manufacturer
Applied Micro Circuits Corporation
Datasheet

Specifications of PPC405EP-3LB333C

Family Name
405EP
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
333MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.8V
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
385
Package Type
BGA
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PPC405EP-3LB333C
Manufacturer:
AMCC
Quantity:
182
PPC405EP – PowerPC 405EP Embedded Processor
Table 8. Package Thermal Specifications
The PPC405EP is designed to operate within a case temperature range of -40°C to +85°C. Thermal resistance values for the E-
PBGA packages in a convection environment are as follows:
Note:
Table 9. Recommended DC Operating Conditions (Sheet 1 of 2)
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Notes:
1. PCI drivers meet PCI specifications.
2. See “5V-Tolerant Input Current” on page 39.
AMCC
Logic Supply Voltage (133, 200, 266MHz)
Logic Supply Voltage (333MHz)
I/O Supply Voltage
PLL Supply Voltage (133, 200, 266MHz)
PLL Supply Voltage (333MHz)
Input Logic High
(1.8V CMOS receivers)
Input Logic High
(3.3V PCI receivers)
Input Logic High
(3.3V LVTTL, 5V tolerant receivers)
Input Logic Low
(1.8V CMOS receivers)
Input Logic Low
(3.3V PCI receivers)
Input Logic Low
(3.3V LVTTL, 5V tolerant receivers)
Output Logic High
(3.3V PCI receivers)
Output Logic High
(3.3V LVTTL, 5V tolerant receivers)
Output Logic Low
(3.3V PCI receivers)
Output Logic Low
(3.3V LVTTL, 5V tolerant receivers)
31mm, 385-balls—Junction-to-Case
31mm, 385-balls—Case-to-Ambient
1. For a chip mounted on a JEDEC 2S2P card without a heat sink.
2. For a chip mounted on a card with at least one signal and two power planes, the following relationships exist:
a. Case temperature, T
b. T
c. T
A
CMax
= T
Package—Thermal Resistance
= T
C
– P
JMax
Parameter
×θ
– P
CA
, where T
×θ
JC
C
, is measured at top center of case surface with device soldered to circuit board.
, where T
A
is ambient temperature and P is power consumption.
1
JMax
is maximum junction temperature and P is power consumption.
Symbol
OV
AV
AV
V
V
V
V
V
V
V
V
V
V
V
V
DD
DD
OH
OH
OL
OL
IH
IH
IH
IL
IL
IL
DD
DD
DD
Minimum
0.5OV
0.9OV
0.65V
Symbol
+1.65
+1.65
+1.7
+3.0
+1.7
+2.0
+2.4
-0.5
-0.5
θ
θ
0
0
0
CA
JC
DD
DD
DD
Typical
0 (0)
+1.8
+1.8
+3.3
+1.8
+1.8
17.8
2
ft/min (m/sec)
100 (0.51)
Maximum
OV
0.35OV
0.35OV
Airflow
0.65V
16.8
Revision 1.08 – March 24, 2008
+1.95
+1.95
OV
OV
+1.9
+3.6
+1.9
+5.5
+0.8
+0.4
V
DD
2
DD
DD
DD
+0.5
DD
DD
DD
200 (1.02)
Data Sheet
16.1
Unit
2
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Notes
°C/W
°C/W
Unit
37

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