MPC9653AAC/W IDT, Integrated Device Technology Inc, MPC9653AAC/W Datasheet
MPC9653AAC/W
Specifications of MPC9653AAC/W
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MPC9653AAC/W Summary of contents
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Freescale Semiconductor, Inc. TECHNICAL DATA 3.3 V 1:8 LVCMOS PLL Clock 3.3 V 1:8 LVCMOS PLL Clock Generator Generator The MPC9653A is a 3.3 V compatible, 1:8 PLL based clock generator and zero-delay buffer targeted for high performance low-skew clock ...
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MPC9653A 3.3 V 1:8 LVCMOS PLL Clock Generator MPC9653A V 2⋅25 k PCLK PCLK FB_IN V CC 3⋅25 k PLL_EN VCO_SEL BYPASS MR/ GND V QFB GND PLL_EN BYPASS VCO_SEL IDT™ 3.3 V 1:8 ...
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MPC9653A 3.3 V 1:8 LVCMOS PLL Clock Generator Table 1. Pin Configuration Pin I/O Type PCLK, PCLK Input LVPECL FB_IN Input LVCMOS VCO_SEL Input LVCMOS BYPASS Input LVCMOS PLL_EN Input LVCMOS MR/OE Input LVCMOS Q0–7 Output LVCMOS QFB Output LVCMOS ...
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MPC9653A 3.3 V 1:8 LVCMOS PLL Clock Generator MPC9653A Table 3. General Specifications Symbol Characteristics V Output Termination Voltage TT MM ESD Protection (Machine Model) HBM ESD Protection (Human Body Model) LU Latch-Up Immunity C Power Dissipation Capacitance PD C ...
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MPC9653A 3.3 V 1:8 LVCMOS PLL Clock Generator Table 6. AC Characteristics (V = 3.3 V ± 5 Symbol Characteristics f Input Reference Frequency REF PLL Mode, External Feedback Input reference frequency in PLL bypass mode f VCO ...
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MPC9653A 3.3 V 1:8 LVCMOS PLL Clock Generator MPC9653A Programming the MPC9653A The MPC9653A supports output clock frequencies from 25 to 125 MHz. Two different feedback divider configurations can be used to achieve the desired frequency operation range. The feedback ...
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MPC9653A 3.3 V 1:8 LVCMOS PLL Clock Generator Calculation of Part-to-Part Skew The MPC9653A zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC9653As ...
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MPC9653A 3.3 V 1:8 LVCMOS PLL Clock Generator MPC9653A MPC9653A OUTPUT BUFFER = 36 Ω Ω IN MPC9653A OUTPUT = 36 Ω BUFFER 14 Ω Ω Figure 6. Single versus ...
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MPC9653A 3.3 V 1:8 LVCMOS PLL Clock Generator t SK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 10. Output-to-Output Skew ...
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MPC9653A PART NUMBERS 3.3 V 1:8 LVCMOS PLL Clock Generator INSERT PRODUCT NAME AND DOCUMENT TITLE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver ...