CY7C4261-10JI Cypress Semiconductor Corp, CY7C4261-10JI Datasheet - Page 9

• Manufacturer Part Number: CY7C4261-10JI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4261-10JI

• Configuration: Dual
• Density: 144Kb
• Access Time (max): 8ns
• Word Size: 9b
• Organization: 16Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: PLCC
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 40mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / Rohs Status: Not Compliant

Switching Waveforms
Notes
Document #: 38-06015 Rev. *D
14. t
15. t
the rising edge of RCLK and the rising edge of WCLK is less than t
the rising edge of WCLK and the rising edge of RCLK is less than t
SKEW1
SKEW1
REN1, REN2
REN1, REN2
(if applicable)
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF goes HIGH during the current clock cycle. If the time between
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF goes HIGH during the current clock cycle. It the time between
Q
D
WEN2
0
0
WEN1
WCLK
WCLK
WEN1
WEN2
RCLK
RCLK
–D
–Q
OE
FF
EF
17
17
t
ENS
t
OLZ
t
SKEW1
t
ENH
t
t
CLKH
CLKH
[14]
t
t
t
WFF
A
REF
t
OE
Figure 6. Write Cycle Timing
Figure 7. Read Cycle Timing
t
t
CLK
CKL
t
SKEW1
SKEW1
SKEW2
NO OPERATION
, then FF may not change state until the next WCLK rising edge.
, then EF may not change state until the next RCLK rising edge.
[15]
t
DS
t
t
CLKL
CLKL
t
ENS
t
VALID DATA
DH
t
ENH
t
REF
t
WFF
t
OHZ
CY7C4261, CY7C4261
NO OPERATION
NO OPERATION
Page 9 of 19
[+] Feedback