Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 307
Z0847006PSG
Manufacturer Part Number
Z0847006PSG
Description
IC 6MHZ Z80 NMOS DART 40-DIP
Manufacturer
Zilog
Series
Z80r
Datasheet
1.Z0847006PSG.pdf
(330 pages)
Specifications of Z0847006PSG
Processor Type
Z80
Features
Dual Channel Asynchronous Receiver/Transmitter (DART)
Speed
6MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Mounting Style
Through Hole
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
847006
Rohs Compliant
Yes
Clock Frequency
6MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z0847006PSG
Manufacturer:
Zilog
Quantity:
22
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UM008101-0601
used for both the receiver and transmitter. The system clock in all modes
must be set to at least 4.5 times the data rate. If the x1 clock rate is selected,
bit synchronization must be performed externally.
Table 25. Clock Rate
Write Register 5
WR5 contains control bits that affect the operation of transmitter, with the
exception of D2, which affects the transmitter and receiver.
Table 26. Write Register 5 Transmitter Control
Transmit CRC Enable (D0)
This bit determines if CRC is calculated on a specific transmit character. If
it is set at the time the character is loaded from the transmit buffer into the
transmit shift register, CRC is calculated on the character. CRC is not auto-
matically sent unless this bit is set when the Transmit Underrun condition
occurs.
D7
DTR
Clock Rate 1
D6
Tx
Bits/
Char 1
0
0
1
1
D5
Tx
Bits/
Char 0
Clock Rate 0 Result
0
1
0
1
D4
Send
Break
Data Rate x1 = Clock Rate
Data Rate x16 = Clock Rate
Data Rate x32 = Clock Rate
Data Rate x64 = Clock Rate
D3
Tx
Enable
D2
CRC-16/
SDLC
Z80 CPU Peripherals
Serial Input/Output
D1
RTS
User Manual
DO
Tx
CRC
Enable
287
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