DS21Q55N Maxim Integrated Products, DS21Q55N Datasheet
DS21Q55N
Specifications of DS21Q55N
Related parts for DS21Q55N
DS21Q55N Summary of contents
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... Connect to Asynchronous Backplanes Up to 16.384MHz § 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz Clock Output Synthesized to Recovered Network Clock ORDERING INFORMATION PART TEMP RANGE DS21Q55 DS21Q55N -40°C to +85°C Pin Configurations appear in Section 2. 237 DS21Q55 PIN-PACKAGE 256 BGA 0°C to +70°C (27mm x 27mm) 256 BGA ...
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... T1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS..........................................50 7 ONTROL EGISTERS 7 RANSMIT RANSPARENCY 7.3 AIS-CI RAI-CI G AND ENERATION AND 7 ECEIVE IDE IGITAL 8. E1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS .........................................59 8 ONTROL EGISTERS 8 UTOMATIC LARM ENERATION 8 NFORMATION EGISTERS 9. COMMON CONTROL AND STATUS REGISTERS ....................................................................66 9.1 T1/ TATUS EGISTERS 10 ...
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T1 Operation ..............................................................................................80 12.1.2 E1 Operation..............................................................................................80 12 ATH ODE IOLATION 12.2.1 T1 Operation ..............................................................................................82 12.2.2 E1 Operation..............................................................................................82 12 RAMES UT OF YNC 12.3.1 T1 Operation ..............................................................................................83 12.3.2 E1 Operation..............................................................................................83 12.4 E-B C ...
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HDLC M ............................................................................................135 APPING 21.3.1 Receive ....................................................................................................135 21.3.2 Transmit ...................................................................................................137 21.3.3 FIFO Information ......................................................................................142 21.3.4 Receive Packet-Bytes Available ...............................................................142 21.3.5 HDLC FIFOs ............................................................................................143 21.4 R HDLC C ECEIVE ODE 21.5 L FDL S EGACY UPPORT 21.5.1 Overview ..................................................................................................144 21.5.2 ...
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JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT...............................198 30.1 D ................................................................................................198 ESCRIPTION 30 NSTRUCTION EGISTER SAMPLE/PRELOAD .............................................................................................202 BYPASS ...............................................................................................................202 EXTEST................................................................................................................202 CLAMP .................................................................................................................202 HIGHZ ..................................................................................................................202 IDCODE................................................................................................................202 30 ...........................................................................................203 EST EGISTERS 30 OUNDARY CAN ...
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... Figure 1-1. Block Diagram ..........................................................................................................................................14 Figure 1-2. Receive and Transmit LIU........................................................................................................................15 Figure 1-3. Receive and Transmit Framer/HDLC.......................................................................................................16 Figure 1-4. Backplane Interface..................................................................................................................................17 Figure 2-1. DS21Q55 PIN DIAGRAM, 27mm BGA ....................................................................................................35 Figure 5-1. Programming Sequence ..........................................................................................................................45 Figure 6-1. Clock Map ................................................................................................................................................49 Figure 14-1. Simplified Diagram of Receive Signaling Path.......................................................................................87 Figure 14-2 ...
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Figure 31-17. G.802 Timing, E1 Mode Only.............................................................................................................216 Figure 31-18. Transmit-Side Timing .........................................................................................................................216 Figure 31-19. Transmit-Side Boundary Timing (Elastic Store Disabled)..................................................................217 Figure 31-20. Transmit-Side Boundary Timing, TSYSCLK = 1.544MHz (Elastic Store Enabled) ..........................217 Figure 31-21. Transmit-Side Boundary Timing, TSYSCLK = 2.048MHz ...
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Table 2-A. Pin Description Sorted by Pin Number .....................................................................................................29 Table 3-A. Register Map Sorted by Address ..............................................................................................................36 Table 7-A. T1 Alarm Criteria .......................................................................................................................................58 Table 8-A. E1 Sync/Resync Criteria ...........................................................................................................................60 Table 8-B. E1 Alarm Criteria.......................................................................................................................................65 Table 12-A. T1 Line Code Violation ...
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... Transmitter 50mA short-circuit limiter with current-limit-exceeded indication § Transmit open-circuit-detected indication § Line interface function can be completely decoupled from the framer/formatter Clock Synthesizer § Output frequencies include 2.048MHz, 4.096MHz, 8.192MHz, and 16.384MHz § Derived from recovered receive clock Jitter Attenuator § ...
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... Signaling freezing § Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode § Access to the data streams in between the framer/formatter and the elastic stores § User-selectable synthesized clock output HDLC Controllers § Two independent HDLC controllers per port § ...
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The DS21Q55 is compliant with the following standards: ANSI: T1.403-1995, T1.231–1993, T1.408 AT&T: TR54016, TR62411 ITU: G.703, G.704, G.706, G.736, G.775, G.823, G.932, I.431, O.151, Q.161 ITU-T: Recommendation I.432–03/93 B-ISDN User-Network Interface—Physical Layer Specification ETSI: ETS 300 011, ETS 300 ...
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... Each transceiver has two HDLC controllers. The HDLC controllers transmit and receive data through the framer block. The HDLC controllers can be assigned to any time slot, group of time slots or a portion of a time slot. The HDLC controllers can also be assigned to the FDL (T1 bits (E1). Each controller has 128-byte FIFOs, thus reducing the amount of processor overhead required to manage the flow of data ...
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Reader’s Note: This data sheet assumes a particular nomenclature of the T1 operating environment. In each 125ms frame there are 24 8-bit channels plus a framing bit assumed that the framing bit is sent first followed by channel ...
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... Block Diagram Figure 1-1 shows a simplified block diagram featuring the major components of the DS21Q55. Details are shown in subsequent figures. The block diagram is divided into three functional blocks: LIU, FRAMER, and BACKPLANE INTERFACE. Figure 1-1. Block Diagram RRING RTIP TRING TTIP ...
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Figure 1-2. Receive and Transmit LIU 32.768MHz RRING RTIP TRING TTIP VCO / PLL MUX 15 of 237 RCL MUX JACLK RPOS RNEG RCLK TPOS TNEG TCLK ...
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... Figure 1-3. Receive and Transmit Framer/HDLC RPOS RNEG RCLK TPOS TNEG TCLK REC HDLC #1 128 Byte FIFO MAPPER DATA RECEIVE CLOCK FRAMER SYNC SYNC TRANSMIT CLOCK FRAMER DATA MAPPER XMIT HDLC #1 128 Byte FIFO 16 of 237 REC HDLC #2 128 Byte FIFO ...
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Figure 1-4. Backplane Interface DATA CLOCK SYNC SYNC Sa/FDL DATA INSERT CLOCK JACLK Sa BIT/FDL EXTRACTION SIGNALING BUFFER ELASTIC STORE CHANNEL TIMING SIGNALING BUFFER ELASTIC STORE CHANNEL TIMING TCLK MUX 17 of 237 RLINK RLCLK RSIG RSIGFR RSYSCLK RSER RCLK ...
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PIN FUNCTION DESCRIPTION 2.1.1 Transmit Side Signal Name: TCLKx Signal Description: Transmit Clock Signal Type: Input A 1.544MHz (T1 2.048MHz (E1) primary clock. Used to clock data through the transmit-side formatter. TCLK can be internally sourced from ...
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Signal Name: TLCLKx Signal Description: Transmit Link Clock Signal Type: Output Demand clock for the transmit link data [TLINK] input. T1 Mode: A 4kHz or 2kHz (ZBTSI) clock. E1 Mode: A 4kHz to 20kHz clock. Signal Name: TLINKx Signal Description: ...
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Signal Name: TPOSOx Signal Description: Transmit Positive-Data Output Signal Type: Output Updated on the rising edge of TCLKO with the bipolar data out of the transmit-side formatter. Can be programmed to source NRZ data by the output data format (IOCR1.0) ...
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... E1 Mode: A 4kHz to 20kHz clock. Signal Name: RCLKx Signal Description: Receive Clock Signal Type: Output 1.544MHz (T1) or 2.048MHz (E1) clock that is used to clock data through the receive-side framer. Signal Name: RCHCLKx Signal Description: Receive Channel Clock Signal Type: Output A 192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel. Synchronous with RCLK when the receive-side elastic store is disabled ...
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Signal Name: RFSYNCx Signal Description: Receive Frame Sync Signal Type: Output An extracted 8kHz pulse, one RCLK wide, is output at this pin that identifies frame boundaries. Signal Name: RMSYNCx Signal Description: Receive Multiframe Sync Signal Type: Output An extracted ...
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... Signal Description: Receive Positive-Data Input Signal Type: Input Sampled on the falling edge of RCLKI for data to be clocked through the receive-side framer. RPOSI and RNEGI can be connected together for an NRZ interface. Can be internally connected to RPOSO by connecting the LIUC pin high. Signal Name: ...
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Parallel Control Port Pins INT Signal Name: Signal Description: Interrupt Signal Type: Output Flags host controller during conditions and events defined in the status registers. Active-low, open-drain output. Signal Name: TSTRST Signal Description: Tri-State Control and Device Reset Signal ...
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CS Signal Name: Signal Description: Chip Select Signal Type: Input Must be low to read or write to transceiver #1 of the device. CS1 is an active-low signal. Signal Name: CS2 Signal Description: Chip Select for transceiver #2 Signal Type: ...
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JTAG Test Access Port Pins Signal Name: JTRST Signal Description: IEEE 1149.1 Test Reset Signal Type: Input JTRST is used to asynchronously reset the test access port controller. After power-up, JTRST must be toggled from low to high. This ...
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... Line Interface Connect Signal Type: Input Connect low to separate the line interface circuitry from the framer/formatter circuitry and activate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. Connect high to connect the line interface circuitry to the framer/formatter circuitry and deactivate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. When LIUC is connected high, the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins should be connected low ...
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Supply Pins Signal Name: DVDD Signal Description: Digital Positive Supply Signal Type: Supply 3.3V ±5%. Should be connected to the RVDD and TVDD pins. Signal Name: RVDD Signal Description: Receive Analog Positive Supply Signal Type: Supply 3.3V ±5%. Should ...
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Pinout The DS21Q55 is available in a 256-pin, 27mm, 1.27-pitch BGA package. Table 2-A. Pin Description Sorted by Pin Number NOTE: Signal is common to all transceivers unless otherwise stated. PIN NAME U3 A0 L17 ...
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... Receive Channel Block, Transceiver #4 O Receive Channel Clock, Transceiver #1 O Receive Channel Clock, Transceiver #2 O Receive Channel Clock, Transceiver #3 O Receive Channel Clock, Transceiver #4 O Receive Clock Output from the Framer, Transceiver #1 O Receive Clock Output from the Framer, Transceiver # 237 FUNCTION ...
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... Receive Negative Data for the Framer, Transceiver #1 I Receive Negative Data for the Framer, Transceiver #2 I Receive Negative Data for the Framer, Transceiver #3 I Receive Negative Data for the Framer, Transceiver #4 O Receive Negative Data from the LIU, Transceiver #1 O Receive Negative Data from the LIU, Transceiver #2 O ...
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... RVSS3 V20 RVSS4 I Receive Positive Data for the Framer, Transceiver #3 I Receive Positive Data for the Framer, Transceiver #4 O Receive Positive Data from the LIU, Transceiver #1 O Receive Positive Data from the LIU, Transceiver #2 O Receive Positive Data from the LIU, Transceiver #3 ...
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... Transmit Positive Data Input for the LIU, Transceiver #3 I Transmit Positive Data Input for the LIU, Transceiver #4 O Transmit Positive Data Output from Framer, Transceiver #1 O Transmit Positive Data Output from Framer, Transceiver #2 O Transmit Positive Data Output from Framer, Transceiver #3 ...
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PIN NAME TYPE Y2 TRING1 Y4 TRING2 Y6 TRING3 Y8 TRING4 W9 TSER1 C17 TSER2 C10 TSER3 K20 TSER4 W10 TSIG1 C18 TSIG2 A10 TSIG3 L19 TSIG4 W12 TSSYNC1 B18 TSSYNC2 D10 TSSYNC3 K19 TSSYNC4 U16 TSTRST V1 TSYNC1 D20 ...
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Package Figure 2-1. DS21Q55 Pin Diagram, 27mm BGA The diagram shown below is the lead pattern that will be placed on the target PC board. This is the same pattern that would be seen as viewed from the top. ...
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PARALLEL PORT The DS21Q55 is controlled via a nonmultiplexed (MUX = multiplexed (MUX = 1) bus by an external microcontroller or microprocessor. The DS21Q55 can operate with either Intel or Motorola bus timing configurations. If the ...
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ADDRESS 20 Status Register 6 21 Interrupt Mask Register 6 22 Status Register 7 23 Interrupt Mask Register 7 24 Status Register 8 25 Interrupt Mask Register 8 26 Status Register 9 27 Interrupt Mask Register 9 28 Per-Channel Pointer ...
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ADDRESS 4C Per-Channel Loopback Enable Register 2 4D Per-Channel Loopback Enable Register 3 4E Per-Channel Loopback Enable Register 4 4F Elastic Store Control Register 50 Transmit Signaling Register 1 51 Transmit Signaling Register 2 52 Transmit Signaling Register 3 53 ...
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ADDRESS 78 Line Interface Control 1 79 Line Interface Control 2 7A Line Interface Control 3 7B Line Interface Control 4 7C Test Register 7D Transmit Line Build-Out Control 7E Idle Array Address Register 7F Per-Channel Idle Code Value Register ...
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ADDRESS A4 HDLC #2 Receive Channel Select 3 A5 HDLC #2 Receive Channel Select 4 A6 HDLC #2 Receive Time Slot Bits/Sa Bits Select A7 HDLC #2 Transmit Channel Select 1 A8 HDLC #2 Transmit Channel Select 2 A9 HDLC ...
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ADDRESS D0 Transmit Align Frame Register D1 Transmit Nonalign Frame Register D2 Transmit Si Align Frame D3 Transmit Si Nonalign Frame D4 Transmit Remote Alarm Bits D5 Transmit Sa4 Bits D6 Transmit Sa5 Bits D7 Transmit Sa6 Bits D8 Transmit ...
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ADDRESS FC Reserved FD Reserved FE Reserved FF Reserved *TEST registers are used only by the factory. REGISTER NAME 42 of 237 REGISTER PAGE ABBREVIATION — — — — — — — — ...
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SPECIAL PER-CHANNEL REGISTER OPERATION Some of the features described in the data sheet that operate on a per-channel basis use a special method for channel selection. There are five registers involved: per-channel pointer register (PCPR) and per- channel data ...
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Register Name: PCDR1 Register Description: Per-Channel Data Register 1 Register Address: 29h Bit # 7 6 Name — — Default CH8 CH7 Register Name: PCDR2 Register Description: Per-Channel Data Register 2 Register Address: 2Ah Bit # 7 6 Name — ...
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PROGRAMMING MODEL The DS21Q55 register map is divided into three groups: T1 specific features, E1 specific features, and common features. The typical programming sequence begins with issuing a reset to the device, selecting operation in the ...
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... A reset clears all configuration and status registers. The bit automatically clears itself when the reset has completed. Bit 1/Device Operating Mode (T1/E1). Used to select the operating mode of the framer/formatter (digital) portion of the 2156. The operating mode of the LIU must also be programmed. ...
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Interrupt Handling Various alarms, conditions, and events in the DS21Q55 can cause interrupts. For simplicity, these are all referred to as events in this explanation. All status registers can be programmed to produce interrupts. Each status register has an ...
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Information Registers Information registers operate the same as status registers except they cannot cause interrupts. They are all latched except for INFO7 and some of the bits in INFO5 and INFO6. INFO7 register is a read-only register. It reports ...
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... FRAMER LOOPBACK LOOPBACK JAS = 0 AND DJA = 0 FLB = 0 LTCA JAS = 1 FLB = 1 OR DJA = 1 RLB = 1 LTCA RLB = 0 Transmit Clock Source 49 of 237 8 x PLL PAYLOAD LOOPBACK (SEE NOTES) BPCLK SYNTH RECEIVE FRAMER PLB = 1 TRANSMIT FORMATTER PLB = 0 TCLK MUX TSYSCLK 8XCLK BPCLK RCLK TCLK ...
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... T1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS The T1 framer portion of the DS21Q55 is configured through a set of nine control registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS21Q55 has been initialized, the control registers only need to be accessed when there is a change in the system configuration ...
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Register Name: T1RCR2 Register Description: T1 Receive Control Register 2 Register Address: 04h Bit # 7 6 Name — RFM Default 0 0 Bit 0/Receive-Side D4 Yellow Alarm Select (RD4YM bit 2 of all channels 1 ...
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Register Name: T1TCR1 Register Description: T1 Transmit Control Register 1 Register Address: 05h Bit # 7 6 Name TJC TFPT Default 0 0 Bit 0/Transmit Yellow Alarm (TYEL not transmit yellow alarm 1 = transmit yellow alarm ...
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Register Name: T1TCR2 Register Description: T1 Transmit Control Register 2 Register Address: 06h Bit # 7 6 Name TB8ZS TSLC96 Default 0 0 Bit 0/Transmit-Side Bit 7 Zero-Suppression Enable (TB7ZS stuffing occurs 1 = bit 7 forced ...
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... TCD1 and TCD2 Bit 1/Pulse Density Enforcer Enable (PDE). The framer always examines the transmit and receive data streams for violations of these, which are required by ANSI T1.403: No more than 15 consecutive 0s and at least each and every time window bits, where through 23 ...
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T1 Transmit Transparency The software signaling insertion-enable registers, SSIE1–SSIE4, can be used to select signaling insertion from the transmit signaling registers, TS1–TS12 per-channel basis. Setting a bit in the SSIEx register allows signaling data to be sourced ...
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T1 Receive-Side Digital-Milliwatt Code Generation Receive-side digital-milliwatt code generation involves using the receive digital-milliwatt registers (T1RDMR1/2/3) to determine which of the 24 T1 channels of the T1 line going to the backplane should be overwritten with a digital-milliwatt pattern. ...
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Register Name: INFO1 Register Description: Information Register 1 Register Address: 10h Bit # 7 6 Name RPDV TPDV Default 0 0 Bit 0/Frame Bit-Error Event (FBE). Set when an Ft (D4) or FPS (ESF) framing bit is received in error. ...
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Table 7-A. T1 Alarm Criteria ALARM Blue Alarm (AIS) (Note 1) Yellow Alarm (RAI) D4 Bit 2 Mode (T1RCR2 12th F-Bit Mode (T1RCR2 this mode is also referred to as the “Japanese Yellow Alarm”) ESF ...
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... E1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS The E1 framer portion of the DS21Q55 is configured by a set of four control registers. Typically, the control registers are only accessed when the system is first powered up. Once the device has been initialized, the control registers need only to be accessed when there is a change in the system configuration ...
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... Bit 0/Receive Carrier-Loss (RCL) Alternate Criteria (RCLA). Defines the criteria for a receive carrier-loss condition for both the framer and LIU RCL declared upon 255 consecutive 0s (125µ RCL declared upon 2048 consecutive 0s (1ms) Bits 1, 2/Unused, must be set to 0 for proper operation Bit 3/Sa4 Bit Select (Sa4S). Set have RLCLK pulse at the Sa4 bit position ...
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Register Name: E1TCR1 Register Description: E1 Transmit Control Register 1 Register Address: 35h Bit # 7 6 Name TFPT T16S Default 0 0 Bit 0/Transmit CRC4 Enable (TCRC4 CRC4 disabled 1 = CRC4 enabled Bit 1/Transmit G.802 Enable ...
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Register Name: E1TCR2 Register Description: E1 Transmit Control Register 2 Register Address: 36h Bit # 7 6 Name Sa8S Sa7S Default 0 0 Bit 0/Automatic Remote Alarm Generation (ARA disabled 1 = enabled Bit 1/Automatic AIS Generation (AAIS) ...
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... CRC4 multiframe synchronization cannot be found within 128ms of FAS synchronization (if CRC4 is enabled). If any one or more of these conditions is present, then the framer transmits an RAI alarm. RAI generation conforms to ETS 300 011 specifications and a constant remote alarm is transmitted if the device cannot find CRC4 multiframe synchronization within 400ms as per G ...
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... CRC4 level. The counter can also be cleared by disabling the CRC4 mode (E1RCR1.3 = 0). This counter is useful for determining the amount of time the framer has been searching for synchronization at the CRC4 level. ITU G.706 suggests that if synchronization at the CRC4 level cannot be obtained within 400ms, then the search should be abandoned and proper action taken. The CRC4 sync counter rolls over. CSC0 is the LSB of the 6-bit counter. (Note: The bit next to LSB is not accessible. CSC1 is omitted to allow resolution to > ...
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Table 8-B. E1 Alarm Criteria ALARM SET CRITERIA An RLOS condition exists on power-up prior to initial synchronization, when a RLOS resync criteria has been met, or when a manual resync has been initiated by E1RCR1.0 RCL 255 or 2048 ...
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COMMON CONTROL AND STATUS REGISTERS Register Name: CCR1 Register Description: Common Control Register 1 Register Address: 70h Bit # 7 6 Name MCLKS CRC4R Default 0 0 Bit 0/Function of the RLOS/LOTC Output (RLOSF receive loss of ...
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... Bit 0/Receive Loss-of-Sync Condition (RLOS). Set when the device is not synchronized to the received data stream. Bit 1/Framer Receive Carrier-Loss Condition (FRCL). Set when 255 (or 2048 if E1RCR2 mode or 192 T1 mode consecutive 0s have been detected at RPOSI and RNEGI. Bit 2/Receive Unframed All-Ones (T1 Blue Alarm, E1 AIS) Condition (RUA1). Set when an unframed all 1s code is received at RPOSI and RNEGI ...
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... Bit 4/Receive Loss-of-Sync Clear Event (RLOSC interrupt masked 1 = interrupt enabled Bit 5/Framer Receive Carrier Loss Condition Clear (FRCLC interrupt masked 1 = interrupt enabled Bit 6/Receive Unframed All-Ones Condition Clear Event (RUA1C interrupt masked 1 = interrupt enabled ...
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Register Name: SR3 Register Description: Status Register 3 Register Address: 1Ah Bit # 7 6 Name LSPARE LDN Default 0 0 Bit 0/Receive Remote Alarm Condition (RRA) (E1 Only). Set when a remote alarm is received at RPOSI and RNEGI. ...
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Register Name: IMR3 Register Description: Interrupt Mask Register 3 Register Address: 1Bh Bit # 7 6 Name LSPARE LDN Default 0 0 Bit 0/Receive Remote Alarm Condition (RRA interrupt masked 1 = interrupt enabled—interrupts on rising and falling ...
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Register Name: SR4 Register Description: Status Register 4 Register Address: 1Ch Bit # 7 6 Name RAIS-CI RSAO Default 0 0 Bit 0/Receive Align Frame Event (RAF) (E1 Only). Set every 250µs at the beginning of align frames. Used to ...
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Register Name: IMR4 Register Description: Interrupt Mask Register 4 Register Address: 1Dh Bit # 7 6 Name RAIS-CI RSAO Default 0 0 Bit 0/Receive Align Frame Event (RAF interrupt masked 1 = interrupt enabled Bit 1/Receive CRC4 Multiframe ...
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I/O PIN CONFIGURATION OPTIONS Register Name: IOCR1 Register Description: I/O Configuration Register 1 Register Address: 01h Bit # 7 6 Name RSMS RSMS2 Default 0 0 Bit 0/Output Data Format (ODF bipolar data at TPOSO and TNEGO ...
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Register Name: IOCR2 Register Description: I/O Configuration Register 2 Register Address: 02h Bit # 7 6 Name RCLKINV TCLKINV Default 0 0 Bit 0/RSYSCLK Mode Select (RSCLKM RSYSCLK is 1.544MHz RSYSCLK is 2.048MHz or ...
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... TSER. The FAS word; Si, Sa, and E bits; and CRC4 are not looped back; they are reinserted by the device. Bit 2/Remote Loopback (RLB). In this loopback, data input by the RPOSI and RNEGI pins is transmitted back to the TPOSO and TNEGO pins. Data continues to pass through the receive-side framer of the device as it would normally. Data from the transmit-side formatter is ignored. See ...
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... Bit 4/Line Interface Unit Mux Control (LIUC). This is a software version of the LIUC pin. When the LIUC pin is connected high, the LIUC bit has control. When the LIUC pin is connected low, the framer and LIU are separated and the LIUC bit has no effect ...
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Per-Channel Loopback The per-channel loopback registers (PCLRs) determine which channels (if any) from the backplane should be replaced with the data from the receive side or, i.e., off of the line. If this loopback is enabled, ...
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Register Name: PCLR3 Register Description: Per-Channel Loopback Enable Register 3 Register Address: 4Dh Bit # 7 6 Name CH24 CH23 Default 0 0 Bits 0 to 7/Per-Channel Loopback Enable for Channels (CH17 to CH24 loopback ...
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ERROR COUNT REGISTERS The device contains four counters that are used to accumulate line-coding errors, path errors, and synchronization errors. Counter update options include one-second boundaries, 42ms (T1 mode only), 62ms (E1 mode only), or manual. See Error-Counter Configuration ...
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... BPVs. If ERCNT.3 is set, then the LVC counts code violations as defined in ITU O.161. Code violations are defined as consecutive bipolar violations of the same polarity. In most applications, the framer should be programmed to count BPVs when receiving AMI code and to count CVs when receiving HDB3 code. This counter increments at all times and is not disabled by loss-of-sync conditions ...
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Register Name: LCVCR1 Register Description: Line-Code Violation Count Register 1 Register Address: 42h Bit # 7 6 Name LCVC15 LCVC14 Default 0 0 Bits 0 to 7/Line-Code Violation Counter Bits (LCVC8 to LCVC15). LCV15 is the MSB ...
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... The path code violation count register records Ft, Fs, or CRC6 errors in T1 frames. When the receive side of a framer is set to operate in the T1 ESF framing mode, PCVCR records errors in the CRC6 codewords. When set to operate in the T1 D4 framing mode, PCVCR counts errors in the Ft framing bit position. ...
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... The FOSCR counts word errors in the FAS in time slot 0. This counter is disabled when RLOS is high. FAS errors are not counted when the framer is searching for FAS alignment and/or synchronization at either the CAS or CRC4 multiframe level. Since the maximum FAS word error count in a one-second period is 4000, this counter cannot saturate ...
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E-Bit Counter (EBCR) This counter is only available in E1 mode. E-bit count register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of a 16-bit counter that records far-end block errors (FEBE) as ...
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DS0 MONITORING FUNCTION The device has the ability to monitor one DS0 64kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction, the user determines which channel ...
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Register Name: RDS0SEL Register Description: Receive Channel Monitor Select Register Address: 76h Bit # 7 6 Name — — Default 0 0 Bits 0 to 4/Receive Channel Monitor Bits (RCM0 to RCM4). RCM0 is the LSB of a 5-bit channel ...
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SIGNALING OPERATION There are two methods to access receive signaling data and provide transmit signaling data, processor- based (software-based) or hardware-based. Processor-based refers to access through the transmit and receive signaling registers RS1–RS16 and TS1–TS16. Hardware-based refers to the ...
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Hardware-Based Receive Signaling In hardware-based signaling the signaling data can be obtained from the RSER pin or the RSIG pin. RSIG is a signaling PCM stream output on a channel-by-channel basis from the signaling buffer. The signaling data, T1 ...
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Register Name: SIGCR Register Description: Signaling Control Register Register Address: 40h Bit # 7 6 Name GRSRE — Default 0 0 Bit 0/Force Receive Signaling All Ones (FRSAO mode, this bit forces all signaling data at the RSIG ...
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Register Name: RS1 to RS12 Register Description: Receive Signaling Registers (T1 Mode, ESF Format) Register Address: 60h to 6Bh (MSB) CH2-A CH2-B CH2-C CH4-A CH4-B CH4-C CH6-A CH6-B CH6-C CH8-A CH8-B CH8-C CH10-A CH10-B CH10-C CH12-A CH12-B CH12-C CH14-A CH14-B ...
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Register Name: RS1 to RS16 Register Description: Receive Signaling Registers (E1 Mode, CAS Format) Register Address: 60h to 6Fh (MSB CH2-A CH2-B CH2-C CH4-A CH4-B CH4-C CH6-A CH6-B CH6-C CH8-A CH8-B CH8-C CH10-A CH10-B CH10-C CH12-A CH12-B ...
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Register Name: RSCSE1, RSCSE2, RSCSE3, RSCSE4 Register Description: Receive Signaling Change-of-State Interrupt Enable Register Address: 3Ch, 3Dh, 3Eh, 3Fh (MSB) CH8 CH7 CH6 CH16 CH15 CH14 CH24 CH23 CH22 CH30 Setting any of the CH1–CH30 bits in the RSCSE1–RSCSE4 registers ...
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... framing mode, there are only two signaling bits per channel (A and B framing mode, the framer uses the C and D bit positions as the A and B bit positions for the next multiframe mode, two multiframes of signaling data can be loaded into TS1–TS12. ...
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E1 Mode In E1 mode, TS16 carries the signaling information. This information can be in either CCS (common channel signaling) or CAS (channel associated signaling) format. The 32 time slots are referenced by two different channel number schemes in ...
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Register Name: TS1 to TS16 Register Description: Transmit Signaling Registers (E1 Mode, CAS Format) Register Address: 50h to 5Fh (MSB CH2-A CH2-B CH2-C CH4-A CH4-B CH4-C CH6-A CH6-B CH6-C CH8-A CH8-B CH8-C CH10-A CH10-B CH10-C CH12-A CH12-B ...
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Register Name: TS1 to TS12 Register Description: Transmit Signaling Registers (T1 Mode, ESF Format) Register Address: 50h to 5Bh (MSB) CH2-A CH2-B CH2-C CH4-A CH4-B CH4-C CH6-A CH6-B CH6-C CH8-A CH8-B CH8-C CH10-A CH10-B CH10-C CH12-A CH12-B CH12-C CH14-A CH14-B ...
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Software Signaling Insertion-Enable Registers, E1 CAS Mode In E1 CAS mode, the CAS signaling alignment/alarm byte can be sourced from the transmit signaling registers along with the signaling data. Register Name: SSIE1 Register Description: Software Signaling Insertion Enable 1 ...
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Register Name: SSIE3 Register Description: Software Signaling Insertion Enable 3 Register Address: 0Ah Bit # 7 6 Name CH22 CH21 Default 0 0 Bit 0/Lower CAS Align/Alarm Word (LCAW). Selects the lower CAS align/alarm bits (xyxx sourced from ...
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... TSIG pin inserted into them on a per-channel basis. See Section 4 for details on using this per-channel (THSCS) feature. The signaling insertion capabilities of the framer are available whether the transmit- side elastic store is enabled or disabled. If the elastic store is enabled, the backplane clock (TSYSCLK) can be either 1 ...
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PER-CHANNEL IDLE CODE GENERATION Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. When operated in the T1 mode, only the first 24 channels are used by the device, ...
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Idle-Code Programming Examples Example 1 Sets transmit channel 3 idle code to 7Eh. Write IAAR = 02h ;select channel 3 in the array Write PCICR = 7Eh ;set idle code to 7Eh Example 2 Sets transmit channels 3, 4, ...
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Register Name: IAAR Register Description: Idle Array Address Register Register Address: 7Eh Bit # 7 6 Name GRIC GTIC Default 0 0 Bits 0 to 5/Channel Pointer Address Bits (IAA0 to IAA5). These bits select the channel to be programmed ...
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The transmit-channel idle-code enable registers (TCICE1/2/3/4) are used to determine which of the channels from the backplane to the line should be overwritten with the code placed in the per-channel code array. ...
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The receive-channel idle-code enable registers (RCICE1/2/3/4) are used to determine which of the channels from the backplane to the line should be overwritten with the code placed in the per-channel code array. ...
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CHANNEL BLOCKING REGISTERS The receive channel blocking registers (RCBR1/RCBR2/RCBR3/RCBR4) and the transmit channel blocking registers (TCBR1/TCBR2/TCBR3/TCBR4) control RCHBLK and TCHBLK pins, respectively. The RCHBLK and TCHBLK pins are user-programmable outputs that can be forced either high or low during ...
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Register Name: RCBR3 Register Description: Receive Channel Blocking Register 3 Register Address: 8Ah Bit # 7 6 Name CH24 CH23 Default 0 0 Bits 0 to 7/Receive Channels Channel Blocking Control Bits (CH17 to CH24 ...
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Register Name: TCBR1 Register Description: Transmit Channel Blocking Register 1 Register Address: 8Ch Bit # 7 6 Name CH8 CH7 Default 0 0 Bits 0 to 7/Transmit Channels Channel Blocking Control Bits (CH1 to CH8 ...
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ELASTIC STORES OPERATION The DS21Q55 contains dual two-frame elastic stores, one for the receive direction and one for the transmit direction. Both elastic stores are fully independent. The transmit and receive-side elastic stores can be enabled/disabled independently of each ...
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Register Name: ESCR Register Description: Elastic Store Control Register Register Address: 4Fh Bit # 7 6 Name TESALGN TESR Default 0 0 Bit 0/Receive Elastic Store Enable (RESE elastic store is bypassed 1 = elastic store is enabled ...
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Register Name: SR5 Register Description: Status Register 5 Register Address: 1Eh Bit # 7 6 Name — — Default 0 0 Bit 0/Receive Elastic Store Slip-Occurrence Event (RSLIP). Set when the receive elastic store has either repeated or deleted a ...
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... TS16 is realigned to the multiframe sync input on RSYNC. Otherwise, a multiframe sync input on RSYNC is treated as a simple frame boundary by the elastic store. The framer always indicates frame boundaries on the network side of the elastic store by the RFSYNC output, whether the elastic store is enabled or not. Multiframe boundaries are always indicated by the RMSYNC output ...
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... TSYNC must be configured as an output when transmit minimum delay mode is enabled typical application, RSYSCLK and TSYSCLK are locked to RCLK, and RSYNC (frame output mode) is connected to TSSYNC (frame input mode). All of the slip contention logic in the framer is disabled (since slips cannot occur). On power-up, after the RSYSCLK and TSYSCLK signals have locked to their respective network clock signals, the elastic store reset bits (ESCR ...
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G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY) The DS21Q55 can implement the G.706 CRC-4 recalculation at intermediate path points. When this mode is enabled, the data stream presented at TSER already has the FAS/NFAS, CRC multiframe alignment word, and ...
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T1 BIT-ORIENTED CODE (BOC) CONTROLLER The DS21Q55 contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1 mode. 19.1 Transmit BOC Bits ...
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Register Name: BOCC Register Description: BOC Control Register Register Address: 37h Bit # 7 6 Name — — Default 0 0 Bit 0/Send BOC (SBOC). Set = 1 to transmit the BOC code placed in bits ...
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Register Name: SR8 Register Description: Status Register 8 Register Address: 24h Bit # 7 6 Name — — Default 0 0 Bit 0/Receive BOC Detector Change-of-State Event (RBOC). Set whenever the BOC detector sees a change of state to a ...
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... Data in the Si bit position is overwritten if either the framer is (1) programmed to source the Si bits from the TSER pin, (2) in the CRC4 mode, or (3) has automatic E-bit insertion enabled. Data in the Sa bit position is overwritten if any of the E1TCR2 ...
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Register Name: RAF Register Description: Receive Align Frame Register Register Address: C6h Bit # 7 6 Name Si 0 Default 0 0 Bit 0/Frame Alignment Signal Bit (1) Bit 1/Frame Alignment Signal Bit (1) Bit 2/Frame Alignment Signal Bit (0) ...
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Register Name: TAF Register Description: Transmit Align Frame Register Register Address: D0h Bit # 7 6 Name Si 0 Default 0 0 Bit 0/Frame Alignment Signal Bit (1) Bit 1/Frame Alignment Signal Bit (1) Bit 2/Frame Alignment Signal Bit (0) ...
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Method 3: Internal Register Scheme Based on CRC4 Multiframe The receive side contains a set of eight registers (RSiAF, RSiNAF, RRA, and RSa4–RSa8) that report the Si and Sa bits as they are received. These registers are updated with ...
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Register Name: RSiNAF Register Description: Received Si Bits of the Nonalign Frame Register Address: C9h Bit # 7 6 Name SiF15 SiF13 Default 0 0 Bit 0/Si Bit of Frame 1 (SiF1) Bit 1/Si Bit of Frame 3 (SiF3) Bit ...
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Register Name: RSa4 Register Description: Received Sa4 Bits Register Address: CBh Bit # 7 6 Name RSa4F15 RSa4F13 Default 0 0 Bit 0/Sa4 Bit of Frame 1 (RSa4F1) Bit 1/Sa4 Bit of Frame 3 (RSa4F3) Bit 2/Sa4 Bit of Frame ...
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Register Name: RSa6 Register Description: Received Sa6 Bits Register Address: CDh Bit # 7 6 Name RSa6F15 RSa6F13 Default 0 0 Bit 0/Sa6 Bit of Frame 1 (RSa6F1) Bit 1/Sa6 Bit of Frame 3 (RSa6F3) Bit 2/Sa6 Bit of Frame ...
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Register Name: RSa8 Register Description: Received Sa8 Bits Register Address: CFh Bit # 7 6 Name RSa8F15 RSa8F13 Default 0 0 Bit 0/Sa8 Bit of Frame 1 (RSa8F1) Bit 1/Sa8 Bit of Frame 3 (RSa8F3) Bit 2/Sa8 Bit of Frame ...
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Register Name: TSiNAF Register Description: Transmit Si Bits of the Nonalign Frame Register Address: D3h Bit # 7 6 Name TSiF15 TSiF13 Default 0 0 Bit 0/Si Bit of Frame 1 (TSiF1) Bit 1/Si Bit of Frame 3 (TSiF3) Bit ...
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Register Name: TSa4 Register Description: Transmit Sa4 Bits Register Address: D5h Bit # 7 6 Name TSa4F15 TSa4F13 Default 0 0 Bit 0/Sa4 Bit of Frame 1 (TSa4F1) Bit 1/Sa4 Bit of Frame 3 (TSa4F3) Bit 2/Sa4 Bit of Frame ...
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Register Name: TSa6 Register Description: Transmit Sa6 Bits Register Address: D7h Bit # 7 6 Name TSa6F15 TSa6F13 Default 0 0 Bit 0/Sa6 Bit of Frame 1 (TSa6F1) Bit 1/Sa6 Bit of Frame 3 (TSa6F3) Bit 2/Sa6 Bit of Frame ...
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Register Name: TSa8 Register Description: Transmit Sa8 Bits Register Address: D9h Bit # 7 6 Name TSa8F15 TSa8F13 Default 0 0 Bit 0/Sa8 Bit of Frame 1 (TSa8F1) Bit 1/Sa8 Bit of Frame 3 (TSa8F3) Bit 2/Sa8 Bit of Frame ...
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Register Name: TSACR Register Description: Transmit Sa Bit Control Register Register Address: DAh Bit # 7 6 Name SiAF SiNAF Default 0 0 Bit 0/Additional Bit 8 Insertion Control Bit (Sa8 not insert data from the TSa8 ...
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HDLC CONTROLLERS This device has two enhanced HDLC controllers, HDLC #1 and HDLC #2. Each controller is configurable for use with time slots, Sa4 to Sa8 bits (E1 mode), or the FDL (T1 mode). Each HDLC controller has 128-byte ...
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Table 21-A. HDLC Controller Registers REGISTER CONTROL AND CONFIGURATION H1TC, HDLC #1 Transmit Control Register H2TC, HDLC #2 Transmit Control Register H1RC, HDLC #1 Receive Control Register H2RC, HDLC #2 Receive Control Register H1FC, HDLC #1 FIFO Control Register H2FC, ...
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Register Name: H1TC, H2TC Register Description: HDLC #1 Transmit Control HDLC #2 Transmit Control Register Address: 90h, A0h Bit # 7 6 Name NOFS TEOML Default 0 0 Bit 0/Transmit CRC Defeat (TCRCD). A 2-byte CRC code is automatically appended ...
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Register Name: H1RC, H2RC Register Description: HDLC #1 Receive Control HDLC #2 Receive Control Register Address: 31h, 32h Bit # 7 6 Name RHR RHMS Default 0 0 Bit 0/Receive SS7 Fill-In Signal Unit Delete (RSFD normal operation; ...
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FIFO Control The FIFO control register (HxFC) controls and sets the watermarks for the transmit and receive FIFOs. Bits 3, 4, and 5 set the transmit low watermark and the lower 3 bits set the receive high watermark. When ...
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HDLC Mapping 21.3.1 Receive The HDLC controllers must be assigned a space in the T1/E1 bandwidth in which they transmit and receive data. The controllers can be mapped to either the FDL (T1), Sa bits (E1 channels. ...
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Register Name: H1RTSBS, H2RTSBS Register Description: HDLC # 1 Receive Time Slot Bits/Sa Bits Select HDLC # 2 Receive Time Slot Bits/Sa Bits Select Register Address: 96h, A6h Bit # 7 6 Name RCB8SE RCB7SE Default 0 0 Bit 0/Receive ...
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Transmit The HxTCS1–HxTCS4 registers are used to assign the transmit controllers to channels 1–24 (T1) or 1–32 (E1) according to the following table. Register Channels HxTCS1 1–8 HxTCS2 9–16 HxTCS3 17–24 HxTCS4 25–32 Register Name: H1TCS1, H1TCS2, H1TCS3, H1TCS4 ...
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Register Name: H1TTSBS, H2TTSBS Register Description: HDLC # 1 Transmit Time Slot Bits/Sa Bits Select HDLC # 2 Transmit Time Slot Bits/Sa Bits Select Register Address: 9Bh, ABh Bit # 7 6 Name TCB8SE TCB7SE Default 0 0 Bit 0/Transmit ...
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Register Name: SR6, SR7 Register Description: HDLC #1 Status Register 6 HDLC #2 Status Register 7 Register Address: 20h, 22h Bit # 7 6 Name — TMEND Default 0 0 Bit 0/Transmit FIFO Not Full Condition (TNF). Set when the ...
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Register Name: IMR6, IMR7 Register Description: HDLC # 1 Interrupt Mask Register 6 HDLC # 2 Interrupt Mask Register 7 Register Address: 21h, 23h Bit # 7 6 Name — TMEND Default 0 0 Bit 0/Transmit FIFO Not Full Condition ...
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Register Name: INFO5, INFO6 Register Description: HDLC #1 Information Register HDLC #2 Information Register Register Address: 2Eh, 2Fh Bit # 7 6 Name — — Default 0 0 Bits 0 to 2/Receive Packet Status (PS0 to PS2). These are real-time ...
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FIFO Information The transmit FIFO buffer-available register indicates the number of bytes that can be written into the transmit FIFO. The count form this register informs the host as to how many bytes can be written into the transmit ...
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HDLC FIFOs Register Name: H1TF, H2TF Register Description: HDLC # 1 Transmit FIFO HDLC # 2 Transmit FIFO Register Address: 9Dh, ADh Bit # 7 6 Name THD7 THD6 Default 0 0 Bit 0/Transmit HDLC Data Bit 0 (THD0). ...
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... In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the receive FDL register (RFDL). Because the RFDL is 8 bits in length, it fills up every 2ms (8 x 250µs). The framer signals an external microcontroller that the buffer has filled through the SR8.3 bit. If enabled through IMR8 ...
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Register Name: RFDL Register Description: Receive FDL Register Register Address: C0h Bit # 7 6 Name RFDL7 RFDL6 Default 0 0 The receive FDL register (RFDL) reports the incoming FDL or the incoming Fs bits. The LSB is received first. ...
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... Bit 7/Transmit FDL Bit 7 (TFDL7). MSB of the transmit FDL code. 21.6 D4/SLC-96 Operation In the D4 framing mode, the framer uses the TFDL register to insert the Fs framing pattern. To allow the device to properly insert the Fs framing pattern, the TFDL register at address C1h must be programmed to 1Ch and the following bits must be programmed as shown: T1TCR1 ...
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... T1 line, and the jitter attenuator. These three sections are controlled by the line interface control registers (LIC1–LIC4), which are described in the following sections. The LIU has its own T1/E1 mode-select bit and can operate independently of the framer function. The DS21Q55 can switch between networks without changing any external components on either the transmit or receive side. In this configuration, the DS21Q55 can connect to T1, J1 (75Ω ...
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Normally, the clock that is output at the RCLK pin is the recovered clock from the E1 AMI/HDB3 or T1 AMI/B8ZS waveform presented at the RTIP and RRING inputs. If the jitter attenuator is placed in the receive path (as ...
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Transmitter The DS21Q55 uses a phase-lock loop along with a precision digital-to-analog converter (DAC) to create the waveforms that are transmitted onto the line. The waveforms created by the DS21Q55 meet the latest ETSI, ITU, ANSI, ...
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MCLK Prescaler A 16.384MHz, 8.192MHz, 4.096MHz, 2.048MHz, or 1.544MHz clock must be applied at MCLK. ITU specification G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specifications require an accuracy of ±32ppm for T1 ...
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LIU Control Registers Register Name: LIC1 Register Description: Line Interface Control 1 Register Address: 78h Bit # 7 6 Name L2 L1 Default 0 0 Bit 0/Transmit Power-Down (TPD powers down the transmitter and tri-states the TTIP ...
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T1 Mode DSX-1 (0ft to 133ft) / 0dB CSU DSX-1 (133ft to 266ft DSX-1 (266ft to 399ft DSX-1 (399ft to 533ft DSX-1 ...
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Register Name: TLBC Register Description: Transmit Line Build-Out Control Register Address: 7Dh Bit # 7 6 Name - AGCE Default 0 0 Bit 0–5 Gain Control Bits 0–5 (GC0–GC5). The GC0 through GC5 bits control the gain setting for the ...
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Register Name: LIC2 Register Description: Line Interface Control 2 Register Address: 79h Bit # 7 6 Name ETS LIRST Default 0 0 Bit 0/Custom Line Driver Select (CLDS). Setting this bit redefines the operation of the transmit ...
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Register Name: LIC3 Register Description: Line Interface Control 3 Register Address: 7Ah Bit # 7 6 Name — TCES Default 0 0 Bit 0/Transmit Alternate Ones and Zeros (TAOZ). Transmit a …101010… pattern (customer disconnect indication signal) at TTIP and ...
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Register Name: LIC4 Register Description: Line Interface Control 4 Register Address: 7Bh Bit # 7 6 Name CMIE CMII Default 0 0 Bits 0, 1/Receive Termination Select (RT0, RT1) RT1 RT0 Internal Receive-Termination Configuration 0 0 Internal receive-side termination disabled ...
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Register Name: INFO2 Register Description: Information Register 2 Register Address: 11h Bit # 7 6 Name BSYNC BD Default 0 0 Bits 0 to 3/Receive Level Bits (RL0 to RL3). Real-time bits RL3 RL2 RL1 ...
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Register Name: SR1 Register Description: Status Register 1 Register Address: 16h Bit # 7 6 Name ILUT TIMER Default 0 0 Bit 0/Loss of Line-Interface Transmit-Clock Condition (LOLITC). Set when TCLKI has not transitioned for one channel time. This is ...
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Register Name: IMR1 Register Description: Interrupt Mask Register 1 Register Address: 17h Bit # 7 6 Name ILUT TIMER Default 0 0 Bit 0/Loss-of-Transmit Clock Condition (LOLITC interrupt masked 1 = interrupt enabled—generates interrupts on rising and falling ...
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Recommended Circuits Figure 22-3. Basic Interface 2:1 TRANSMIT LINE RECEIVE LINE Note 1: All resistor values are ±1%. Note 2: Resistors R should be set to 60Ω each if the internal receive-side termination feature is enabled. When this feature ...
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Figure 22-4. Protected Interface Using Internal Receive Termination 2:1 F1 TRANSMIT LINE X2 F2 1:1 F3 RECEIVE LINE X1 F4 Note 1: All resistor values are ±1%. Note 2: X1 and X2 are very low DCR transformers. Note 3: C1 ...
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Component Specifications Table 22-A. Transformer Specifications SPECIFICATION Turns Ratio 3.3V Applications Primary Inductance Leakage Inductance Intertwining Capacitance Transmit Transformer DC Resistance Primary (Device Side) Secondary Receive Transformer DC Resistance Primary (Device Side) Secondary RECOMMENDED VALUE 1:1 (receive) and 1:2 ...
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Figure 22-5. E1 Transmit Pulse Template 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 Figure 22-6. T1 Transmit Pulse Template 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 ...
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Figure 22-7. Jitter Tolerance 1k 100 10 1 0.1 1 Figure 22-8. Jitter Tolerance (E1 Mode) 1k 100 0.1 1 DS21Q55 TOLERANCE TR 62411 (DEC. 90) ITU-T G.823 10 100 1k FREQUENCY (Hz) DS21Q55 TOLERANCE 1.5 MINIMUM ...
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Figure 22-9. Jitter Attenuation (T1 Mode) 0dB -20dB -40dB -60dB 1 Figure 22-10. Jitter Attenuation (E1 Mode) 0dB -20dB -40dB -60dB 1 DS21Q55 T1 MODE 10 100 1K FREQUENCY (Hz) TBR12 Prohibited Area Prohibited Area DS21Q55 E1 MODE 10 100 ...
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... SR3.5, LDN at SR3.6, and LSPARE at SR3.7) is set Normally codes are sent for a period of five seconds recommended that the software poll the framer every 50ms to 1000ms until five seconds has elapsed to ensure the code is continuously present. ...
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Register Name: IBCC Register Description: In-Band Code Control Register Register Address: B6h Bit # 7 6 Name TC1 TC0 Default 0 0 Bits 0 to 2/Receive Down-Code Length Definition Bits (RDN0 to RDN2) RDN2 RDN1 ...
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Register Name: TCD1 Register Description: Transmit Code-Definition Register 1 Register Address: B7h Bit # 7 6 Name C7 C6 Default 0 0 Bit 0/Transmit Code-Definition Bit 0 (C0). A don’t care if a 5-, 6-, or 7-bit length is selected. ...
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Register Name: RUPCD1 Register Description: Receive Up-Code Definition Register 1 Register Address: B9h Bit # 7 6 Name C7 C6 Default 0 0 Note: Writing this register resets the detector’s integration period. Bit 0/Receive Up-Code Definition Bits 0 (C0). A ...
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Register Name: RDNCD1 Register Description: Receive Down-Code Definition Register 1 Register Address: BBh Bit # 7 6 Name C7 C6 Default 0 0 Note: Writing this register resets the detector’s integration period. Bit 0/Receive Down-Code Definition Bit 0 (C0). A ...
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Register Name: RSCC Register Description: In-Band Receive Spare Control Register Register Address: BDh Bit # 7 6 Name — — Default 0 0 Bits 0 to 2/Receive Spare Code Length Definition Bits (RSC0 to RSC2) RSC2 RSC1 RSC0 0 0 ...
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Register Name: RSCD1 Register Description: Receive Spare-Code Definition Register 1 Register Address: BEh Bit # 7 6 Name C7 C6 Default 0 0 Note: Writing this register resets the detector’s integration period. Bit 0/Receive Spare-Code Definition Bit 0 (C0). A ...
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BERT FUNCTION The BERT block can generate and detect pseudorandom and repeating bit patterns used to test and stress data communication links, and it is capable of generating and detecting the following patterns: § The pseudorandom patterns ...
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... FROM RECEIVE FRAMER PER-CHANNEL AND F-BIT (T1 MODE) MAPPING TO TRANSMIT FRAMER Figure 24-2. Simplified Diagram of BERT in Backplane Direction FROM RECEIVE FRAMER PER-CHANNEL AND F-BIT (T1 MODE) MAPPING TO TRANSMIT FRAMER BERT BERT RECEIVER TRANSMITTER 1 0 BERT BERT RECEIVER TRANSMITTER 174 of 237 TO RECEIVE SYSTEM BACKPLANE ...
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BERT Register Descriptions Register Name: BC1 Register Description: BERT Control Register 1 Register Address: E0h Bit # 7 6 Name TC TINV Default 0 0 Bit 0/Force Resynchronization (RESYNC). A low-to-high transition forces the receive BERT synchronizer to resynchronize ...
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Register Name: BC2 Register Description: BERT Control Register 2 Register Address: E1h Bit # 7 6 Name EIB2 EIB1 Default 0 0 Bits 0 to 3/Repetitive Pattern Length Bit 3 (RPL0 to RPL3). RPL0 is the LSB and RPL3 is ...
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Register Name: SR9 Register Description: Status Register 9 Register Address: 26h Bit # 7 6 Name — BBED Default 0 0 Bit 0/BERT in Synchronization Condition (BSYNC). Set when the incoming pattern matches for 32 consecutive bit positions. Refer to ...
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Register Name: IMR9 Register Description: Interrupt Mask Register 9 Register Address: 27h Bit # 7 6 Name — BBED Default 0 0 Bit 0/BERT in Synchronization Condition (BSYNC interrupt masked 1 = interrupt enabled—interrupts on rising and falling ...
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BERT Repetitive Pattern Set These registers must be properly loaded for the BERT to generate and synchronize to a repetitive pattern, a pseudorandom pattern, alternating word pattern Daly pattern. For a repetitive pattern that is fewer than ...
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BERT Bit Counter Once BERT has achieved synchronization, this 32-bit counter increments for each data bit (i.e., clock) received. Toggling the LC control bit in BC1 can clear this counter. This counter saturates when full and sets the BBCO ...
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BERT Error Counter Once BERT has achieved synchronization, this 24-bit counter increments for each data bit received in error. Toggling the LC control bit in BC1 can clear this counter. This counter saturates when full and sets the BECO ...
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... Bit 1/BERT Direction (BERTDIR network BERT transmits toward the network (TTIP and TRING) and receives from the network (RTIP and RRING). The BERT pattern can be looped back to the receiver internally by using the framer loopback function system BERT transmits toward the system backplane (RSER) and receives from the system backplane (TSER). ...
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PAYLOAD ERROR-INSERTION FUNCTION (T1 MODE ONLY) An error-insertion function is available in the DS21Q55 and is used to create errors in the payload portion of the T1 frame in the transmit path. This function is only available in T1 ...
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Register Name: ERC Register Description: Error-Rate Control Register Register Address: EBh Bit # 7 6 Name WNOE — Default 0 0 Bits 0 to 3/Error-Insertion Rate Select Bits (ER0 to ER3) ER3 ER2 ER1 ER0 ...
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Number-of-Errors Registers The number-of-error registers determine how many errors are generated 1023 errors can be generated. The host loads the number of errors to be generated into the NOE1 and NOE2 registers. The host can also update ...
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Number-of-Errors Left Register The host can read the NOELx registers at any time to determine how many errors are left to be inserted. Register Name: NOEL1 Register Description: Number-of-Errors Left 1 Register Address: EEh Bit # 7 6 Name ...
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... INTERLEAVED PCM BUS OPERATION (IBO) In many architectures, the PCM outputs of individual framers are combined into higher speed PCM buses to simplify transport across the system backplane. The DS21Q55 can be configured to allow PCM data to be multiplexed into higher speed buses eliminating external hardware, saving board space and cost. The DS21Q55 can be configured for channel or frame interleave ...
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Register Name: IBOC Register Description: Interleave Bus Operation Control Register Register Address: C5h Bit # 7 6 Name — IBS1 Default 0 0 Bits 0 to 2/Device Assignment Bits (DA0 to DA2) DA2 DA1 DA0 ...
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Figure 26-1. IBO Example RSYSCLK TSYSCLK RSYNC TSSYNC RSIG TSIG TSER RSER DS21Q55 #1 RSYSCLK TSYSCLK RSYNC TSSYNC RSIG TSIG TSER RSER DS21Q55 #2 189 of 237 8.192MHz SYSTEM CLOCK IN SYSTEM 8kHz FRAME SYNC IN PCM SIGNALING OUT PCM ...
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EXTENDED SYSTEM INFORMATION BUS (ESIB) The extended system information bus (ESIB) allows two DS21Q55s to share an 8-bit CPU bus for reporting alarms and interrupt status as a group. With a single bus read, the host can be updated ...
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Register Name: ESIBCR1 Register Description: Extended System Information Bus Control Register 1 Register Address: B0h Bit # 7 6 Name — — Default 0 0 Bit 0/Extended System Information Bus Enable (ESIEN disabled 1 = enabled Bits 1 ...
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Register Name: ESIBCR2 Register Description: Extended System Information Bus Control Register 2 Register Address: B1h Bit # 7 6 Name — ESI4SEL2 Default 0 0 Bits 0 to 2/Address ESI3 Data Output Select (ESI3SEL0 to ESI3SEL2). These bits select what ...
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Register Name: ESIB1 Register Description: Extended System Information Bus Register 1 Register Address: B2h Bit # 7 6 Name DISn DISn Default 0 0 Bits 0 to 7/Device Interrupt Status (DISn). Causes all devices participating in the ESIB group to ...
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PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER The DS21Q55 contains an on-chip clock synthesizer that generates a user-selectable clock output on the BPCLK pin, referenced to the recovered receive clock (RCLK). The synthesizer uses a phase-locked loop to generate low-jitter clocks. Common ...
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FRACTIONAL T1/E1 SUPPORT The DS21Q55 can be programmed to output gapped clocks for selected channels in the receive and transmit paths to simplify connections into a USART or LAPD controller in fractional T1/E1 or ISDN- PRI applications. The receive ...
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... Bit 7/Transmit Multiframe Sync Source (TMSS). Should be set = 0 only when transmit hardware signaling is enabled elastic store is source of multiframe sync 1 = framer or TSYNC pin is source of multiframe sync CRRUI ...
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Register Name: CCR4 Register Description: Common Control Register 4 Register Address: 73h Bit # 7 6 Name RLT3 RLT2 Default 0 0 Bit 0/Reserved, must be set to 0 for proper operation. Bit 1/ Reserved, must be set to 0 ...
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JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT 30.1 Description The DS2Q155 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE (Figure 30-1.). The DS21Q55 contains the ...
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TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK (Figure 30-2). Test-Logic-Reset Upon power-up, the TAP controller is in the Test-Logic-Reset state. The ...
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Select-IR-Scan All test registers retain their previous state. The instruction register remains unchanged during this state. With JTMS LOW, a rising edge on JTCLK moves the controller into the Capture-IR state and initiates a scan sequence for the instruction register. ...