MT90826AL Zarlink, MT90826AL Datasheet
MT90826AL
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MT90826AL Summary of contents
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... Timing Unit PLLV PLLV DD Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved. MT90826AL MT90826AG MT90826AV MT90826AL1 MT90826AG2 **Pb Free Tin/Silver/Copper Applications • Medium switching platforms • CTI application • Voice/data multiplexer • ...
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... The per stream input and output delay control is particularly useful for managing large multi-chip switches with a distributed backplane. Operating in Split Rate mode allows rate conversion for switching between two groups of bit rate streams. MT90826 2 Zarlink Semiconductor Inc. Data Sheet ...
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... Constant Delay Mode (TM1=1, TM0= 5.0 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.0 Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.0 Connection Memory Control 8.0 DTA Data Transfer Acknowledgment Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.0 Initialization of the MT90826 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10.0 JTAG Support 10.1 Test Access Port (TAP 10.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 MT90826 Table of Contents 3 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 12 - ST-BUS Timing for Stream rate of 2.048 Mbps when CLK = 16.384 MHz . . . . . . . . . . . . . . . . . . . . . 39 Figure 13 - -BUS Timing for Stream rate of 2.048 Mbps when CLK = 8.192 MHz Figure 14 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 15 - Output Driver Enable (ODE Figure 16 - Motorola Non-Multiplexed Bus Timing MT90826 List of Figures 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 11 - Output Offset Bits (FD9, FD2- Table 12 - Bit Error Input Selection (BISR) Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 13 - Bit Error Count (BECR) Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 14 - Connection Memory Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 15 - SAB and CAB Bits Programming for Various Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 MT90826 List of Tables 5 Zarlink Semiconductor Inc. Data Sheet ...
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... Clarified the input data sampling position at 16 Mbps data rate. Added the input data sampling position at 8 Mbps data rate. Added the input data sampling position at 4 Mbps data rate. Added the input data sampling position at 2 Mbps data rate. 6 Zarlink Semiconductor Inc. Data Sheet Change ...
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... D0 D1 149 D2 D3 151 D4 153 D5 D6 155 D7 VSS 157 VDD D8 159 MT90826 109 107 105 103 101 160 Pin MQFP Pin Pitch 0. Figure 2 - 160-Pin MQFP Pin Connections 7 Zarlink Semiconductor Inc. Data Sheet STi9/FEi9 STi8/FEi8 VDD VSS STo7 STo6 STo5 STo4 VSS ...
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... VDD VDD VDD NC PLLVDD A9 A10 A12 DTA R 23mm x 23mm Ball Pitch 1.5mm 8 Zarlink Semiconductor Inc. Data Sheet STo10 STo8 STi10 STi9 STo11 STo9 STi11 STi8 STi13 STi12 STo7 STo5 GND STo3 STo6 STo4 VDD STo2 STi7 STi6 VDD STo1 STi5 STi4 ...
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... VDD GND GND GND GND GND DS VDD VDD VDD D13 R/W A13 A1 A4 A10 DTA Zarlink Semiconductor Inc. Data Sheet STo11 STo9 STi11 STi9 STo10 STo8 STI10 STi8 STi13 STi12 STo7 STo5 GND STo2 STo6 STo4 VDD STo3 STi7 STi6 VDD ...
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... TCK M12 TRST K11 IC1 K10 RESET 10 Zarlink Semiconductor Inc. Data Sheet Description +3.3 Volt Power Supply. Ground. Test Mode Select (3.3 V Input with Internal pull-up). JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pull-up when not driven ...
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... C7,C6,C5,C4 STo16 - 19 A2,B2 STo20, STo21 B1,A1 STo22, STo23 C3,D3,E4,E3 STo24 - 27 F3,G3,G1,G2 STo28 - 31 11 Zarlink Semiconductor Inc. Data Sheet Description Internal Connection 2 (3.3 V Input with internal pull-down). Connect to V for normal operation. SS Internal Connection 3 (3.3 V Input with internal pull-down). Connect to V for normal operation. ...
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... STo0-15 may be set to 16.384 Mbps. Combinations of two bit rates, N and 2N are provided. See Table 1. By using Zarlink’s message mode capability, the microprocessor can access input and output timeslots on a per channel basis. This feature is useful for transferring control and status information for external circuits or other ST- BUS devices ...
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... Zarlink Semiconductor Inc. Data Sheet Output Data Rate STo0-31 8 Mbps STo0-15 16 Mbps STo0-15 4 Mbps STo16-31 8 Mbps STo0-11 16 Mbps STo12-19 8 Mbps STo0-31 4 Mbps STo0-15 2 Mbps STo16-31 4 Mbps STo0-31 2 Mbps ST-BUS Output Driver High-Z Per Channel High-Z Enable Enable Enable A0 Location 0 Control Register, CR ...
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... Zarlink Semiconductor Inc. Data Sheet A0 Location 1 Input Offset Selection Register 5, DOS5 0 Input Offset Selection Register 6, DOS6 1 Input Offset Selection Register 7, DOS7 0 Frame Output Offset Register, FOR0 1 Frame Output Offset Register, FOR1 0 Frame Output Offset Register, FOR2 1 Frame Output Offset Register, FOR3 ...
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... Mbps input to be converted to 8 Mbps output and vice versa. 4 Mbps mode (DR2=1, DR1=0, DR0=0) When the 4 Mbps mode is selected, the device is configured with 32-input/32-output data streams each having 64 64 Kbps channels. This mode allows a maximum non-blocking capacity of 2,048 x 2,048 channels. MT90826 15 Zarlink Semiconductor Inc. Data Sheet ...
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... The frame output offset registers (FOR0 & FOR3) control the output offset delays for each output streams via the programming of the OFn bits. See Table 10 and Table 11 for the frame output offset programming. MT90826 16 Zarlink Semiconductor Inc. Data Sheet ...
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... Location 0 Stream Stream Stream Stream Stream Stream Stream Stream Stream Stream Stream Stream Stream Stream Stream Stream Stream Stream Stream Zarlink Semiconductor Inc. Data Sheet Channel Address (Ch0-255) Channel Location (Note (Note 126 127 (Note 128 129 . . . . . 254 255 (Note 5) -1. ...
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... For data memory read operations, two consecutive microprocessor cycles are required. The read address (A0-A13) should remain the same for the two consecutive read cycles. The data memory content from the first read cycle should be ignored. MT90826 18 Zarlink Semiconductor Inc. Data Sheet ...
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... MBP Memory Block Program. When 1, the connection memory block programming feature is ready to program Bit13 to Bit15 of the connection memory. When 0, feature is disabled. MT90826 , CBER SBER SFE 0 BPE MBP Description Table 5 - Control Register Bits 19 Zarlink Semiconductor Inc. Data Sheet DR2 DR1 DR0 MS OSB ...
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... High impedance state X 0 Per-channel high impedance Serial Interface Mode (CPLL=0) 8 Mbps 16 Mbps 4 and 8 Mbps 16.384 MHz 16 and 8 Mbps 4 Mbps 16.384 MHz 2 and 4 Mbps 2 Mbps 16.384 MHz 20 Zarlink Semiconductor Inc. Data Sheet DR2 DR1 DR0 MS OSB CLK CLK (CPLL=1) 16.384 MHz 8.192 MHz ...
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... Table 7 - Frame Alignment (FAR) Register Bits MT90826 , CFE FD9 FD8 FD7 FD6 Description Internal Master Clock Operation Mode C8i 2 Mbps C16i 4 Mbps, 2&4 Mbps C32i 8 Mbps, 16 Mbps, 4&8 Mbps, 16&8 Mbps 21 Zarlink Semiconductor Inc. Data Sheet FD5 FD4 FD3 FD2 FD1 FD0 ...
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... C32i clock cycles) H (FD9 = 0, sample at internal C32i low phase (FD[8: frame offset of three C16i clock cycles) H (FD9 = 0, sample at internal C16i low phase (FD[8: frame offset of two C8i clock cycles) H (FD9 = 1, sample at internal C8i high phase) For 2 Mbps mode 22 Zarlink Semiconductor Inc. Data Sheet ...
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... IF220 IF213 IF212 IF211 DOS5 register IF262 IF261 IF260 IF252 IF251 IF253 DOS6 register IF302 IF301 IF300 IF292 IF291 IF293 DOS7 register Description 23 Zarlink Semiconductor Inc. Data Sheet IF10 IF02 IF01 IF00 IF03 IF50 IF43 IF42 IF41 IF40 IF90 IF83 IF82 ...
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... DOS4 register IF213 IF222 IF221 IF220 IF212 DOS5 register IF262 IF261 IF260 IF252 IF253 DOS6 register IF302 IF301 IF300 IF293 IF292 DOS7 register Description 24 Zarlink Semiconductor Inc. Data Sheet IF11 IF10 IF02 IF01 IF00 IF03 IF51 IF50 IF43 IF42 IF41 IF40 IF91 ...
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... Table 9 - Frame delay Bits (FD9, FD2-0) and Input Offset Bits (IFn3-0) MT90826 Measurement Result from Corresponding Input Offset Bits Frame Delay Bits FD9 FD2 FD1 FD0 IFn3 Zarlink Semiconductor Inc. Data Sheet IFn2 IFn1 IFn0 ...
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... Internal master clock at 32 MHz 16Mbps STi Stream Bit 7 16Mbps STi Stream Figure 6 - Examples for Input Offset Delay Timing MT90826 Bit 7 Bit 7 Bit 7 denotes the 1/2 point of the 16M bps bit cell 26 Zarlink Semiconductor Inc. Data Sheet IFn=0000 IFn=0100 IFn=0000 IFn=0010 ...
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... FOR2 register OF281 OF280 OF271 OF270 OF261 FOR3 register Description Output Stream Offset for 8 Mbps, 16 Mbps, 4&8 Mbps and 16&8 Mbps modes (Not available for 2 Mbps, 4 Mbps and 2&4 Mbps modes) 27 Zarlink Semiconductor Inc. Data Sheet OF20 OF11 OF10 OF01 OF00 ...
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... BISR register BSA2 BSA1 BSA0 BCA7 BCA6 BCA5 Description for BECR register BER10 BER9 BER8 BER7 BER6 BER5 Description 28 Zarlink Semiconductor Inc. Data Sheet offset=00, (0ns) offset=01, (-15ns BCA4 BCA3 BCA2 BCA1 BCA0 BER4 BER3 BER2 BER1 BER0 ...
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... See Table 14 for the description of the connection memory bits. 8.0 DTA Data Transfer Acknowledgment Pin The DTA pin is driven LOW by internal logic, to indicate to the CPU that a data bus transfer is complete. When the read or write cycle ends, this pin changes to the high-impedance state. MT90826 29 Zarlink Semiconductor Inc. Data Sheet ...
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... TCK pulses. When no data is shifted through the boundary scan cells, the TDO driver is set to a high impedance state. • Test Reset (TRST) Resets the JTAG scan structure. This pin is internally pulled to VDD. MT90826 30 Zarlink Semiconductor Inc. Data Sheet ...
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... The device identification register is a 32-bit register with the register contain of: MSB 0000 0000 1000 0010 0110 0001 0100 1011 The LSB bit in the device identification register is the first bit clock out. The MT90826 scan register contains 165 bits. MT90826 LSB 31 Zarlink Semiconductor Inc. Data Sheet ...
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... STi14 STi15 STo12 43 STo13 45 STo14 47 STo15 49 STi16 STi17 STi18 STi19 STo16 55 STo17 57 STo18 69 61 STo19 STi20 STi21 STi22 STi23 STo20 67 STo21 69 STo22 71 STo23 73 STi24 STi25 STi26 STi27 STo24 79 STo25 81 STo26 83 STo27 85 MT90826 Input Cell Scan Cell Zarlink Semiconductor Inc. Data Sheet ...
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... Zarlink Semiconductor Inc. Data Sheet ...
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... Bit Error Test mode; the pseudo random test pattern will be output on the output channel and stream associated with this location. Table 14 - Connection Memory Bits CAB Bits Used to Determine the Source CAB6 to CAB0 (64 or 128 channel/frame) CAB7 to CAB0 (128 or 256 channel/frame) CAB5 to CAB0 ( channel/frame) 34 Zarlink Semiconductor Inc. Data Sheet CAB ...
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... 0. unless otherwise stated. ss Sym. Min. Typ. Max 100 Zarlink Semiconductor Inc. Data Sheet Min. Max. Units -0 0.3 5 ° +125 Max. Units Test Conditions °C + Units Test Conditions mA Output unloaded V V µA µA 0≤<V≤V ...
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... Units Sym. Min. Typ FPW t 5 FPS t 10 FPH 115 FPW8 t 5 FPS8 t 10 FPH8 t 110 CP8 t 50 CH8 t 50 CL8 Zarlink Semiconductor Inc. Data Sheet Conditions Max. Units CLK 65 ns 16.384 MHz 145 ns 8.192 MHz ns ns 150 +10 ns ...
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... FPW t FPH t IDS_16 Ch0 Ch0 Ch0 Ch0 Bit7 Bit6 Bit5 Bit4 t SIH_16 Ch0 Ch0 Ch0 Ch0 Bit7 Bit6 Bit5 Bit4 37 Zarlink Semiconductor Inc. Data Sheet Typ. Max. Units Test Conditions 183 ns 366 =30pF =200pF =1K, C ...
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... Figure 11 - ST-BUS Timing for Stream rate of 4.096 Mbps when CLK = 8.192 MHz MT90826 Bit 7, Channel 0 Bit 6, Channel 0 Bit 5, Channel SIS SIH Bit 7, Channel 0 Bit 6, Channel IDS_4 Ch0 Bit SIS SIH Ch0 Bit CP8 CL8 Ch0 Bit SIS SIH Ch0 Bit 7 38 Zarlink Semiconductor Inc. Data Sheet Bit 5, Channel Ch0 Bit 6 TT ...
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... Figure 14 - Serial Output and External Control MT90826 IDS_2 Ch0 Bit 7 t SIS Ch0 Bit CP8 CL8 CH8 Ch0 Bit 7 t SIS Ch0 Bit Valid Data HiZ Valid Data HiZ TT 39 Zarlink Semiconductor Inc. Data Sheet Ch0 Bit SIH V Ch0 Bit Ch0 Bit SIH V Ch0 Bit 6 TT ...
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... MT90826 ODE t t ODE ODE Valid Data STo HiZ HiZ Figure 15 - Output Driver Enable (ODE) 40 Zarlink Semiconductor Inc. Data Sheet ...
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... ADS t 0 CSH t 2 RWH t 10 ADH t 27 DDR t 12 DHR DSW SWD t 13 DHW t AKD t AKD t AKH , with timing corrected to cancel time taken to discharge Zarlink Semiconductor Inc. Data Sheet Test Conditions =150pF =150pF Note 185 =150pF L 100 ns C =150pF L ...
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... DS CS R/W A0-A7 D0-D15 READ D0-D15 WRITE DTA Figure 16 - Motorola Non-Multiplexed Bus Timing MT90826 t CSS t RWS t ADS Valid Address Valid Read Data t t DSW SWD Valid Write Data t DDR t AKD 42 Zarlink Semiconductor Inc. Data Sheet CSH RWH ADH DHR DHW AKH ...
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... Zarlink Semiconductor 2002 All rights reserved ISSUE 213834 ACN 213740 11Dec02 15Nov02 DATE APPRD. Package Code Previous package codes ...
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... Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned ...