FDC37N769 Standard Microsystems, FDC37N769 Datasheet
FDC37N769
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FDC37N769 Summary of contents
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... Floppy Disk Available on Parallel Port Pins ACPI Compliant Enhanced Digital Data Separator - 2Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates - Programmable Precompensation Modes SMSC DS – FDC37N769 FEATURES Serial Ports - Two High Speed NS16C550 Compatible UARTs with Send/Receive 16 Byte FIFOs - Supports 230k and 460k Baud ...
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... The FDC37N769 does not require any external filter components, is easy to use and offers lower system cost and reduced board area. The FDC37N769 is software and register compatible with SMSC’s proprietary 82077AA core. ...
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... Read Deleted Data ............................................................................................................................ 47 Read A Track ..................................................................................................................................... 48 Write Data ......................................................................................................................................... 48 Write Deleted Data............................................................................................................................ 49 Verify ................................................................................................................................................. 49 Format A Track ................................................................................................................................. ............................................................................................................................ 51 ONTROL OMMANDS Read ID.............................................................................................................................................. 51 Recalibrate ........................................................................................................................................ 52 Seek.................................................................................................................................................... 52 Sense Interrupt Status........................................................................................................................ 52 Sense Drive Status ............................................................................................................................. 53 Specify ............................................................................................................................................... 53 Configure........................................................................................................................................... 54 Version............................................................................................................................................... 54 SMSC DS – FDC37N769 TABLE OF CONTENTS R ................................................................................. 17 EGISTERS Page 3 of 137 DATASHEET Rev. 02-16-07 ...
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... EPP 1.9 OPERATION ........................................................................................................................... 77 Software Constraints ......................................................................................................................... 78 EPP 1.9 Write.................................................................................................................................... 78 EPP 1.9 Read .................................................................................................................................... 78 EPP 1.7 OPERATION ........................................................................................................................... 79 Software Constraints ......................................................................................................................... 79 EPP 1.7 Write.................................................................................................................................... 79 EPP 1.7 Read .................................................................................................................................... 79 EXTENDED CAPABILITIES PARALLEL PORT .............................................................................. 81 Vocabulary ........................................................................................................................................ 81 ISA IMPLEMENTATION STANDARD ............................................................................................. 82 Description ........................................................................................................................................ 82 Register Definitions ........................................................................................................................... 83 OPERATION ..................................................................................................................................... 88 SMSC DS – FDC37N769 ......................................................................................... 57 ...................................................................................................... 68 O ................................................................................. 71 PERATION T ....................................................................................... 72 IME Page 4 of 137 DATASHEET Rev. 02-16-07 ...
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... CR17................................................................................................................................................ 107 CR18 - CR1D................................................................................................................................... 107 CR1E ............................................................................................................................................... 107 CR1F ............................................................................................................................................... 108 CR20................................................................................................................................................ 108 CR21 - CR22 ................................................................................................................................... 109 CR23................................................................................................................................................ 109 CR24................................................................................................................................................ 109 CR25................................................................................................................................................ 109 CR26................................................................................................................................................ 110 CR27................................................................................................................................................ 110 CR28................................................................................................................................................ 110 CR29................................................................................................................................................ 111 CR2A ............................................................................................................................................... 111 CR2B ............................................................................................................................................... 111 CR2C ............................................................................................................................................... 112 SMSC DS – FDC37N769 ............................................................................................ 97 Page 5 of 137 DATASHEET Rev. 02-16-07 ...
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... DC ELECTRICAL CHARACTERISTICS ......................................................................................... 113 AC TIMING....................................................................................................................................... 116 H T ....................................................................................................................................... 116 OST IMING FDD T ........................................................................................................................................ 120 IMING ........................................................................................................................... 121 ERIAL ORT IMING ...................................................................................................................... 126 ARALLEL ORT IMING Parallel Port EPP Timing .............................................................................................................. 127 Parallel Port ECP Timing .............................................................................................................. 132 PACKAGE OUTLINES ................................................................................................................... 136 SMSC DS – FDC37N769 Page 6 of 137 DATASHEET Rev. 02-16-07 ...
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... DRV2/ADRX/IRQ_B 92 VSS 93 nDACK_C 94 A10 95 IRQIN 96 DRQ_C 97 IOCHRDY 98 DRVDEN0 99 nMTR0 100 FIGURE 1 - FDC37N769 PIN CONFIGURATION SMSC DS – FDC37N769 PIN CONFIGURATION FDC37N769 100 PIN TQFP Page 7 of 137 DATASHEET DRQ_B VSS 45 AEN 44 nIOW 43 nIOR 42 A9 ...
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... Disk nRDATA Data 8 nWrite nWGATE Gate SMSC DS – FDC37N769 PIN DESCRIPTION BUFFER TYPE PER PIN BUFFER TYPE DESCRIPTION HOST PROCESSOR INTERFACE IO12 The data bus connection used by the host microprocessor to transmit data to and from the chip. These pins are in a high-impedance state when not in the output mode ...
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... Data 1 79,89 nRequest nRTS1 to Send nRTS2 (System (SYSOPT) Option) SMSC DS – FDC37N769 BUFFER TYPE DESCRIPTION O12/OD12 This active low high current driver provides the encoded data to the disk drive. Each falling edge causes a flux transition on the media. O12/OD12 This high current output selects the floppy disk side for reading or writing. A logic “ ...
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... Select Input/FDC nStep Pulse 3 (Note ) nSTEP SMSC DS – FDC37N769 BUFFER TYPE O6 Active low Data Terminal Ready outputs for the serial port. Handshake output signal notifies modem that the UART is ready to establish data communication link. This signal can be programmed by writing to bit 0 of Modem Control Register (MCR). The hardware reset will reset the nDTR signal to inactive mode (high) ...
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... Port Data PD2 2/FDC nWrite nWRTPRT Protected SMSC DS – FDC37N769 BUFFER TYPE DESCRIPTION (OD14/OP1 This output is bit 2 of the printer control register. This 4)/OD12 is used to initiate the printer when low. Refer to Parallel Port description for use of this pin in ECP and EPP mode. ...
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... Change 63 Port Data 5 PD5 62 Port Data PD6 6/FDC nMotor On nMTR0 0 61 Port Data 7 PD7 SMSC DS – FDC37N769 BUFFER TYPE DESCRIPTION IOP14/IS Port Data 3 See FDC Pin definition. IOP14/IS Port Data 4 See FDC Pin definition. IOP14 Port Data 5 IOP14/ Port Data 6 OD12 See FDC Pin definition ...
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... Note 3: Active (push-pull) output drivers are required on these pins in the enhanced parallel port modes. Note 4: An external pull-up must be provided for IOCHRDY. Note 5: The pull-down on this pin is always active including when the output driver is tristated and regardless of the state of PWRGD. SMSC DS – FDC37N769 BUFFER TYPE DESCRIPTION ALTERNATE IR PINS/MISC ICLK The external connection to a single source 14 ...
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... IS Input with Schmitt Trigger Output Drivers Active output drivers in the FDC37N769 will always achieve the minimum specified DC Electrical Characteristics shown in TABLE 117. Note: If there is a pull- external node driven by an active output driver the FDC37N769 will sink current from the pull-up through the low impedance source. ...
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... RCLOCK RDATA nDS0,1 nINDEX nDIR nMTR0,1 nTRK0 nSTEP nHDSEL nRDATA nDSKCHG DRVDEN0 nWDATA nWRPRT DRVDEN1 nWGATE DRV2/nADRX/IRQB FIGURE 2 - FDC37N769 BLOCK DIAGRAM Page 15 of 137 DATASHEET nSLCTIN/nSTEP,nINI T/nDIR, nAUTOFD/ nDENSEL, nSTROBE/nDS0, BUSY/nMTR1, MULTI-MODE nACK/nDS1, PARALLEL PE/nWRDATA,nERR PORT/FDC OR/nHDSEL, MUX PD0/nINDEX, PD1/nTRK0, PD2/nWRTPRT, ...
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... Base +[400:403] for ECP Note 1: Configuration registers can only be modified in the configuration state, refer to section CONFIGURATION on page 95 for more information. All logical blocks in the FDC37N769 can operate normally in the Configuration State. Note 2: The base addresses must be set in the configuration registers before accessing the logical device blocks. ...
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... Change configuration register (see section CR17 on page 107). nINDEX, Bit 2 Active low status of the INDEX disk interface input. Head Select, Bit 3 Active high status of the HDSEL disk interface input. A logic “1” selects side 1 and a logic “0” selects side 0. SMSC DS – FDC37N769 REGISTER R Status Register A R ...
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... Model 30 interface mode (Table 8). SRB can be accessed at any time when in these modes. During a read in PC/AT interface mode the data bus pins are held in a high impedance state. PS/2 Interface Mode 7 1 RESET 1 CONDITION SMSC DS – FDC37N769 Table 6 - SRA PS/2 Model 30 Mode DRQ STEP F/F ...
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... DIR register. Write Data, Bit 4 Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE. SMSC DS – FDC37N769 Table 8 - SRB PS/2 Model 30 Mode 6 5 ...
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... This bit controls the MTR1 disk interface output. A logic “1” in this bit will cause the output pin to go active. MOTOR ENABLE 2, Bit 6 The MOTOR ENABLE 2 bit controls the MTR2 disk interface output. A logic “1” in this bit will cause the output pin to go active. SMSC DS – FDC37N769 Table 9 - Digital Output Register 6 5 ...
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... External 2-to-4 Drive decoding expands support for four floppy drives but requires an external 2-to-4 decoder. The drive select encoding is determined by the EXTx4 bit in CR05. The FDC37N769 can also internally swap drive 0 and drive 1 using the Swap Drv 0, 1 bit in CR05. Table 12 illustrates Internal 2-Drive decoding with drive 0 and drive 1 swapped. Table 14 illustrates External 2-to-4 Drive decoding with drive 0 and drive 1 swapped ...
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... The configuration of the TDR in the Enhanced Floppy Mode 2 (OS/2 mode) is shown in Table 17. DB7 DB6 TDR Reserved Reserved, Bits Bits 6 and 7 are RESERVED. Reserved bits cannot be written and return 0 when read. SMSC DS – FDC37N769 DRIVE SELECT (ACTIVE LOW) Bit 4 Bit1 Bit 0 nDS1 ...
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... Indicates the direction of a data transfer once an RQM is set. A “1” indicates a read and a “0” indicates a write is required. RQM, Bit 7 Indicates that the host can transfer data if set to a “1”. No access is permitted if set to a “0”. SMSC DS – FDC37N769 Table 18 - Drive Type ID TDR - DRIVE TYPE ID Bit 0 ...
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... The controller will come out of manual low power mode after a software reset or following access to the Data Register or Main Status Register. Software Reset, Bit 7 This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing. SMSC DS – FDC37N769 Table 20 - Data Rate Select Register 6 5 ...
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... Note 1: This is for DENSEL in normal mode (see section CR05 on page 101). The DENSEL pin is set high after a hardware reset and is unaffected by the DOR and the DSR resets. SMSC DS – FDC37N769 Table 21 - Precompensation Delays PRECOMPENSATION DELAY 0.00 ns-DISABLED ...
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... An overrun or underrun will terminate the current command and the transfer of data. Disk writes will complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result phase may be entered. SMSC DS – FDC37N769 FORMAT (see section CR0B on page 104 to program Drive Rate) 360K, 1 ...
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... The DSK CHG bit monitors the pin of the same name and reflects the opposite value seen on the disk cable. The DSK CHG bit also depends upon the Force Disk Change bits in the Force FDD Status Change register (see section CR17 on page 107). SMSC DS – FDC37N769 Table 25 - Example FIFO Service Delays EXAMPLE DATA RATES 1Mbps 1 x 8μ ...
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... These bits determine the data rate of the floppy controller. See Table 22 for the appropriate values. Reserved, Bits Bits are RESERVED. Reserved bits cannot be written and return 0 when read. Model 30 Interface Mode 7 RESET N/A CONDITION SMSC DS – FDC37N769 Table 28 - DIR Model 30 Interface Mode ...
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... ND No Data 1 NW Not Writable SMSC DS – FDC37N769 Table 31 - Status Register 0 DESCRIPTION 00 - Normal termination of command. The specified command was properly executed and completed without error Abnormal termination of command. Command execution was started, but was not successfully completed Invalid command. The requested command could not be executed. ...
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... MD Missing Data Address Mark SMSC DS – FDC37N769 DESCRIPTION Any one of the following: 1. The FDC did not detect an ID address mark at the specified track after encountering the index pulse from the IDX pin twice. 2. The FDC cannot detect a data address mark or a deleted data address mark on the specified track ...
Page 31
... Select Reset There are three sources of system reset on the FDC: the RESET pin of the FDC37N769, a reset generated via a bit in the DOR, and a reset generated via a bit in the DSR. At power on, a Power On Reset initializes the FDC. All resets take the FDC out of the power down state. ...
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... FDRQ goes inactive after nDACK goes active for the last byte of a data transfer (or on the active edge of nIOW of the last byte edge is present on nDACK). A data overrun may occur if FDRQ is not removed in time to prevent an unwanted cycle. SMSC DS – FDC37N769 Page 32 of 137 DATASHEET ...
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... invalid, an interrupt is issued. The user sends a Sense Interrupt Status command which returns an invalid command error. Refer to Table 35 for explanations of the various symbols used. Table 36 lists the required parameters and the results associated with each command that the FDC is capable of performing. SMSC DS – FDC37N769 Page 33 of 137 DATASHEET ...
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... HUT Head Unload Time LOCK MFM MFM/FM Mode Selector MT Multi-Track Selector SMSC DS – FDC37N769 DESCRIPTION The currently selected address 255. The pattern to be written in each sector data field during formatting. Designates which drives are perpendicular Perpendicular Mode Command. A “1” indicates a perpendicular drive. If this bit is “ ...
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... Status 2 ST3 Status 3 WGATE Write Gate SMSC DS – FDC37N769 DESCRIPTION This specifies the number of bytes in a sector. If this parameter is “00”, then the sector size is 128 bytes. transferred is determined by the DTL parameter. Otherwise the sector size is (2 raised to the “N’th” power) times 128. All values up to “ ...
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... W MT MFM Execution Result SMSC DS – FDC37N769 Table 36 - Instruction Set READ DATA DATA BUS HDS DS1 DS0 ──────── C ──────── ...
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... MT MFM Execution Result SMSC DS – FDC37N769 READ DELETED DATA DATA BUS HDS DS1 DS0 ──────── C ──────── ...
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... W MT MFM Execution Result SMSC DS – FDC37N769 WRITE DELETED DATA DATA BUS HDS DS1 ──────── C ──────── ...
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... Command Execution Result SMSC DS – FDC37N769 READ A TRACK DATA BUS MFM HDS DS1 ──────── C ──────── ...
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... W W Execution Result PHASE R/W D7 Command W 0 Result R 1 SMSC DS – FDC37N769 VERIFY DATA BUS HDS DS1 ──────── C ──────── ...
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... Repeat Result PHASE R/W D7 Command Execution SMSC DS – FDC37N769 FORMAT A TRACK DATA BUS MFM HDS DS1 ──────── N ──────── ...
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... Result R PHASE R/W D7 Command Execution SMSC DS – FDC37N769 SENSE INTERRUPT STATUS DATA BUS ─────── ST0 ─────── ─────── PCN ─────── ...
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... LOCK PHASE R/W D7 Command Execution Result R SMSC DS – FDC37N769 CONFIGURE DATA BUS EIS EFIFO POLL ─── FIFOTHR ─── ───────── PRETRK ───────── ...
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... ST0 ─────── Page 44 of 137 DATASHEET Disk status after the Command has completed REMARKS D0 0 Command Codes WGATE REMARKS Invalid Command Codes (NoOp - FDC37N769 goes into Standby State) ST0 = 80H Rev. 02-16-07 ...
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... For reads, it continues to read the entire 128-byte sector and checks for CRC errors. For writes, it completes the 128-byte sector by filling in zeros not set to 00 Hex, DTL should be set to FF Hex and has no impact on the number of bytes transferred. SMSC DS – FDC37N769 LOCK DATA BUS ...
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... Except where noted in Table 39, the value of the sector address is automatically incremented (see Table 41 SMSC DS – FDC37N769 Table 37 - Sector Sizes N SECTOR SIZE 00 128 bytes 01 256 bytes 02 512 bytes 03 1024 bytes .. ... 07 16 Kbytes ...
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... Except where noted in Table 40 the value of the sector address is automatically incremented (see Table 41).Table 40 - Skip Bit vs. Read Deleted Data Command. SK BIT DATA ADDRESS VALUE ENCOUNTERED 0 Normal Data 0 Deleted Data 1 Normal Data 1 Deleted Data SMSC DS – FDC37N769 SECTOR CM BIT OF READ? ST2 SET? Yes No Yes Yes Yes No No Yes SECTOR ...
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... Transfer Capacity EN (End of Cylinder) bit ND (No Data) bit Head Load, Unload Time Interval ID information when the host terminates the command Definition of DTL when and when N does not = 0 SMSC DS – FDC37N769 Table 41 - Result Phase Table HOST ID INFORMATION AT RESULT PHASE C NC Equal to EOT ...
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... After formatting each sector, the host must send new values for and N to the FDC for the next sector on the track. The R value (sector number) is the only value that must be changed by the host after each sector is formatted. This allows the disk to be formatted with nonsequential sector addresses (interleaving). This incrementing and SMSC DS – FDC37N769 SC/EOT VALUE Success Termination ...
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... IAM GAP 40x 6x 26x GAP4 SYN IAM GAP 80x 12x 50x SMSC DS – FDC37N769 Table 43 - FORMAT FIELDS SYSTEM 34 (DOUBLE DENSITY) FORMAT SYN IDAM GAP 12x 22x ...
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... The following commands will generate an interrupt upon completion. They do not return any result bytes highly recommended that control commands be followed by the Sense Interrupt Status command. Otherwise, valuable interrupt status information will be lost. SMSC DS – FDC37N769 Table 44 - Typical Values for Formatting SECTOR SIZE ...
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... FDC requires a data transfer during the execution phase in the non-DMA mode The Sense Interrupt Status command resets the interrupt signal and, via the IC code and SE bit of Status Register 0, identifies the cause of the interrupt SMSC DS – FDC37N769 “1” (step in) and issues step pulses. “0” (step out) and issues step pulses. ...
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... Head Load signal goes high and the read/write operation starts. The values change with the data rate speed selection and are documented in Table 46. The values are the same for MFM and FM. SMSC DS – FDC37N769 Table 45 - Interrupt Identification ...
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... The Version command checks to see if the controller is an enhanced type or the older type (765A). A value returned as the result byte. Relative Seek The command is coded the same as for Seek, except for the MSB of the first byte and the DIR bit. SMSC DS – FDC37N769 Table 46 - Drive Control Delays (ms) HUT 500K ...
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... Gap2 field size. For both cases, and approximate two-byte cushion is maintained from the beginning of the sync field for the purposes of avoiding write splices in the presence of motor speed variation. SMSC DS – FDC37N769 Table 47 - Head Step Direction Control DIR ...
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... The DUMPREG command is designed to support system run-time diagnostics and application software development and debug. To accommodate the LOCK command and the enhanced PERPENDICULAR MODE command the eighth byte of the DUMPREG command has been modified to contain the additional data from these two commands. SMSC DS – FDC37N769 Table 48 - Affects of WGATE and GAP Bits LENGTH OF GAP2 ...
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... COMPATIBILITY The FDC37N769 was designed with software compatibility in mind fully backwards-compatible solution with the older generation 765A/B disk controllers. The FDC also implements on-board registers for compatibility with the PS/2, as well as PC/AT and PC/XT, floppy disk controller subsystems. After a hardware reset of the FDC, all registers, functions and enhancements default to a PC/AT, PS/2 or PS/2 Model 30 compatible operating mode, depending on how the IDENT and MFM bits are configured by the system BIOS ...
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... Addressing of the accessible registers of the Serial Port is shown below (Table 51). The base addresses of the serial ports are defined by the configuration registers (see section CONFIGURATION on page 95). The Serial Port registers are located at sequentially increasing addresses above these base addresses. The FDC37N769 contains two serial ports, each of which contain a register set as described below. 1 ...
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... Disabling the interrupt system inhibits the Interrupt Identification Register and disables any Serial Port interrupt out of the FDC37N769. All other system functions operate in their normal manner, including the Line Status and MODEM Status Registers. The contents of the Interrupt Enable Register are described below. ...
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... REGISTER BIT BIT BIT BIT SMSC DS – FDC37N769 Table 52 - Interrupt Control INTERRUPT SET AND RESET FUNCTIONS PRIORITY INTERRUPT 0 LEVEL TYPE 1 - None 0 Highest Receiver Line Status 0 Second Received Data Available 0 Second Character Time-out ...
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... The RCVR Trigger bits are used to set the trigger level for the RCVR FIFO interrupt (Table 53). Bit LINE CONTROL REGISTER (LCR) The Line Control register (Address Offset = 3H, DLAB = 0, READ/WRITE) contains the formatting information for the serial line. SMSC DS – FDC37N769 INTERRUPT SET AND RESET FUNCTIONS PRIORITY INTERRUPT 0 LEVEL TYPE 0 Fourth ...
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... The Word Length Select bits specify the number of bits in each transmitted or received serial character. Note: the Start, Stop and Parity bits are not included in the word length. The encoding of the Word Length bits is shown in Table 54. SMSC DS – FDC37N769 Table 54 - Word Length Encoding WORD LENGTH ...
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... Request To Send, Bit 1 The Request To Send bit controls the Request To Send (nRTS) output. . nRTS output is forced to a logic “0”. When bit logic “0”, the nRTS output is forced to a logic “1”. SMSC DS – FDC37N769 Table 55 - STOP Bit Encoding STOP BITS ...
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... The FE is reset to a logic “0” whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular SMSC DS – FDC37N769 Page 64 of 137 DATASHEET Rev ...
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... Delta Data Carrier Detect, Bit 3 The Delta Data Carrier Detect (DDCD) bit indicates that the nDCD input to the chip has changed state. Note: Whenever bits are set to a logic “1”, a MODEM Status Interrupt is generated. SMSC DS – FDC37N769 Page 65 of 137 DATASHEET ...
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... Table 56 - Baud Rates Using 1.8462 MHz Clock DIVISOR USED TO DESIRED GENERATE 16X BAUD RATE CLOCK 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 SMSC DS – FDC37N769 PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL* 2307 0.03 1538 0.03 1049 0.005 858 0.01 769 0.03 384 0.16 192 0.16 96 0.16 64 ...
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... DIVISOR USED TO DESIRED GENERATE 16X BAUD RATE CLOCK 9600 19200 38400 57600 115200 230400 460800 SMSC DS – FDC37N769 PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL* 12 0.16 6 0.16 3 0.16 2 1.6 1 0.16 32770 0.16 32769 0.16 Page 67 of 137 DATASHEET CROC: BIT Rev. 02-16-07 ...
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... When a time-out interrupt has not occurred the time-out timer is reset after a new character is received or after the CPU reads the RCVR FIFO. When the XMIT FIFO and transmitter interrupts are enabled (FCR bit 0 = “1”, IER bit 1 = “1”), XMIT interrupts occur as follows: SMSC DS – FDC37N769 Table 57 - RESET Function RESET CONTROL RESET ...
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... DLAB = 1 ADDR = 1 Divisor Latch (MS) DLAB = 1 *DLAB is Bit 7 of the Line Control Register (ADDR = 3). Note 1: Bit 0 is the least significant bit the first bit serially transmitted or received. SMSC DS – FDC37N769 The transmitter interrupt after changing FCR0 will be REGISTER SYMBOL BIT 0 RBR ...
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... Note 3: This bit no longer has a pin associated with it. Note 4: When operating in the XT mode, this register is not available. Note 5: These bits are always zero in the non-FIFO mode. Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip. SMSC DS – FDC37N769 BIT 4 BIT 5 Data Bit 4 ...
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... These FIFO related features allow optimization of CPU/UART transactions and are especially useful given the higher baud rate capability (256K baud). INFRARED INTERFACE The FDC37N769 infrared interface provides a two-way wireless communications port using infrared as the transmission medium. Several infrared protocols have been provided in this implementation including IrDA v1.1 (SIR/FIR), ASKIR, and Consumer IR ( ...
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... This interface supports two types of external FIR transceiver modules. One uses a mode pin (IR Mode) to program the data rate, while the other has a second Rx data pin (IRR3). The FDC37N769 uses Pin 21 for these functions. Pin 21 has IR Mode and IRR3 as its first and second alternate function, respectively. These functions are selected through CR29 as shown in Table 60 ...
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... IrCC Block RAW COM TV ASK OUT IrDA FIR AUX COM G.P. Data Fast Bit FIGURE 3 - INFRARED INTERFACE BLOCK DIAGRAM SMSC DS – FDC37N769 The Half Duplex Time-out is programmable from 0 to 25.5ms in 100μs TX1 0 RX1 1 1 TX2 1 RX2 2 0 TX3 RX3 IR M ODE ...
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... PARALLEL PORT The FDC37N769 incorporates an IBM XT/AT compatible parallel port. The FDC37N769 supports the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the FDC37N769 Configuration Registers and the following hardware configuration description for information on disabling, powering down, changing the base address, and selecting the mode of operation of the parallel port ...
Page 75
... RESET. Writing a one to this bit clears the time out status bit write, this bit is self clearing and does not require a write of a zero. Writing a zero to this bit has no effect. BITS are not implemented as register bits, during a read of the Printer Status Register these bits are a low level. SMSC DS – FDC37N769 Table 63 - Parallel Port Connector STANDARD ...
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... This bit is output onto the nINIT output without inversion. BIT 3 SLCTIN - PRINTER SELECT INPUT This bit is inverted and output onto the nSLCTIN output. A logic “1” on this bit selects the printer; a logic “0” means the printer is not selected. SMSC DS – FDC37N769 Page 76 of 137 DATASHEET Rev. 02-16-07 ...
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... The timer indicates if more than 10μsec have elapsed from the start of the EPP cycle (nIOR or nIOW asserted) to nWAIT being deasserted (after command time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in Status bit 0. SMSC DS – FDC37N769 Page 77 of 137 DATASHEET When the Rev ...
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... Peripheral tri-states the PData bus and asserts nWAIT, indicating to the host that the PData bus is tri-stated. 10. Chip may modify nWRITE, PDIR and nPDATA in preparation for the next cycle. SMSC DS – FDC37N769 peripheral should latch the information byte now. PData bus for the SData bus, deasserts ...
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... EPP SIGNAL EPP NAME nWRITE nWrite PD<0:7> Address/Data INTR Interrupt SMSC DS – FDC37N769 Table 64 - EPP Pin Descriptions TYPE DESCRIPTION O This signal is active low. It denotes a write operation. I/O Bi-directional EPP byte wide address and data bus. I This signal is active high and positive edge triggered. (Pass through with no inversion, Same as SPP) ...
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... Direction Note 1: SPP and EPP can use 1 common register. Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle. For correct EPP read cycles, PCD is required low. SMSC DS – FDC37N769 TYPE DESCRIPTION I This signal is active low. ...
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... MODE 1 Note These registers are available in all modes. 2 Note All FIFOs use one common 16 byte FIFO. SMSC DS – FDC37N769 Table 65 - ECP Registers PD6 PD5 PD4 Address or RLE field nAck PError Select 0 Direction ackIntEn Parallel Port Data FIFO ...
Page 82
... NAutoFd O (HostAck) NFault I (nPeriphRequest) SMSC DS – FDC37N769 Table 66 - ECP Pin Descriptions DESCRIPTION During write operations nStrobe registers data or address into the slave on the asserting edge (handshakes with Busy). Contains address or data or RLE data. Indicates valid data driven by the peripheral when asserted. This signal handshakes with nAutoFd in reverse ...
Page 83
... The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports. During a READ operation, PD0 - PD7 ports are read and output to the host CPU. SMSC DS – FDC37N769 DESCRIPTION Sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction ...
Page 84
... BIT 4 ackIntEn - INTERRUPT REQUEST ENABLE The interrupt request enable bit when set to a high level may be used to Parallel Port to the CPU due to a low to high transition on the nACK input. Refer to the description of the interrupt under Operation, Interrupts. SMSC DS – FDC37N769 Page 84 of 137 DATASHEET enable interrupt requests from the Rev ...
Page 85
... Data bytes are always read from the head of tFIFO regardless of the value of the direction bit. For example if 44h, 33h, 22h is written to the FIFO, then reading the tFIFO will return 44h, 33h, 22h in the same order as was written. SMSC DS – FDC37N769 Page 85 of 137 DATASHEET Rev ...
Page 86
... This bit shall be set to “1” whenever there are writeIntrThreshold or more bytes free in the FIFO. case dmaEn=0 direction=1: This bit shall be set to “1” whenever there are readIntrThreshold or more valid bytes to be read from the FIFO. SMSC DS – FDC37N769 Page 86 of 137 DATASHEET ...
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... All drivers have active pull-ups (push-pull). 111: Configuration Mode. In this mode the confgA, confgB registers are accessible at 0x400 and 0x401. All drivers have active pull-ups (push-pull). SMSC DS – FDC37N769 Table 69 - Extended Control Register MODE Page 87 of 137 DATASHEET ...
Page 88
... When in the reverse direction, normal data is transferred when PeriphAck is high and an 8 bit command is transferred when PeriphAck is low. The most significant bit of the command is always zero. Reverse channel addresses are seldom used and may not be supported in hardware. SMSC DS – FDC37N769 Page 88 of 137 DATASHEET ...
Page 89
... Table 70 - Forward Channel Commands (HostAck Low) Reverse Channel Commands (PeripAck Low) Data The FDC37N769 supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Run length encoded (RLE) compression in hardware is not supported. To transfer compressed data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo. ...
Page 90
... The ECP requests programmed I/O transfers from the host by activating the PINTR pin. The programmed I/O will empty or fill the FIFO using the appropriate direction and mode. Note: A threshold equivalent to a threshold of 15. These two cases are treated the same. SMSC DS – FDC37N769 nd cycle, PDRQ must be kept unasserted until nPDACK ...
Page 91
... FIFO in a single burst. This process is repeated until the last byte is transferred into the FIFO. AUTO POWER MANAGEMENT Power management is provided for the following FDC37N769 logical devices: Floppy Disk, UART1, UART2 and the Parallel Port. For each logical device two types of power management are provided; direct powerdown and auto powerdown. ...
Page 92
... Consequently, the behavior of the device pins during powerdown very important. The pins of the FDC37N769 FDC can be divided into two major categories: system interface and floppy disk drive interface. When the FDC is powered down, the floppy disk drive pins are disabled so that no power will be drawn through the part as a result of any voltage applied to the pin within the part’ ...
Page 93
... System Interface Pins Table 72 gives the state of the system interface pins in the powerdown state. Pins unaffected by the powerdown are labeled “Unchanged”. Input pins are “Disabled” to prevent them from causing currents internal to the FDC37N769 when they have indeterminate input values. ...
Page 94
... Parallel port Auto Power Management is enabled by the Parallel Port Enable bit in Configuration Register 7 (see section CR07 on page 102). When set, this bit allows the ECP or EPP logical parallel port blocks to be placed into the powerdown state as follows: SMSC DS – FDC37N769 STATE IN AUTO POWERDOWN Input Pins ...
Page 95
... CONFIGURATION The configuration of the FDC37N769 is programmed through hardware selectable Configuration Access Ports that appear when the chip is placed into the configuration state. The FDC37N769 logical device blocks, if enabled, will operate normally in the configuration state. Configuration Access Ports The Configuration Access Ports are the CONFIG PORT, the INDEX PORT, and the DATA PORT (Table 74) ...
Page 96
... Exiting the Configuration State To exit the configuration state, write one byte of AAH data to the CONFIG PORT. The FDC37N769 will automatically deactivate the Configuration Access Ports following this procedure, at which point configuration register access cannot occur until the configuration state is explicitly re-enabled. ...
Page 97
... Configuration Select Register (CSR) The Configuration Select Register can only be accessed when the FDC37N769 is in the configuration state. The CSR is located at the INDEX PORT address and must be initialized with configuration register index before the register can be accessed using the DATA PORT. ...
Page 98
... To disable the host address registers the logical device’s base address must be set below 100h. Devices that are powered down but still reside at a valid I/O base address will participate in Plug-and-Play range checking. SMSC DS – FDC37N769 DB6 DB5 ...
Page 99
... IRQ_B 1 2 NOTE : See NOTE in section CR05 on page 101. SMSC DS – FDC37N769 Table 78 - CR02 DESCRIPTION Read Only. A read returns “0” high level on this bit, allows normal operation of the Primary Serial Port (Default). A low level on this bit places the Primary Serial Port into Power Down Mode. Read Only. A read returns “ ...
Page 100
... Note : The function of this bit has been modified from the FDC37C669. This bit’s former function, the selection of the pins for IR receive and transmit, has been moved to CR0A. SMSC DS – FDC37N769 DESCRIPTION Bit 0 If CR1 bit low level then: 0 Standard and Bi-directional Modes (SPP) (default) ...
Page 101
... Note : In the FDC37N769, the behavior of the DRVDEN1 Control CR03.4 depends upon the FDC Output Control CR05.1 (Table 82). If the FDC Output Control is active DRVDEN1 will behave as described in the 669FR; i.e., if CR03 the DRVDEN1 output pin assumes the value of the DRVDEN1 function, if CR03 the DRVDEN1 output pin stays high ...
Page 102
... Floppy Boot 2 Reserved 3 Reserved 4 Parallel Port Enable 5 UART 2 Enable 6 UART 1 Enable 7 Floppy Disk Enable SMSC DS – FDC37N769 Table 82 - DRVDEN1 Control DRVDEN1 (PIN 18) 0 1/0 NORMAL DRVDEN1 FUNCTION 1 1 DRVDEN1 FORCED HIGH X TRISTATE ALL FDD OUTPUT PINS ARE TRISTATED Table 83 - DR06: Drive Type ID Register ...
Page 103
... Note: The function of the IR OUTPUT MUX bits and how they are reset has been modified from the FDC37C669. The first two options were previously selected through CR04. SMSC DS – FDC37N769 ADRA5 ADRA4 Reserved Table 87 - ADRx Configuration Bits ...
Page 104
... UART 2 XMIT 2 UART 2 Duplex This bit is used to define the FULL/HALF DUPLEX UART 2 MODE UART 2 Mode 6 UART 1 Speed This bit enables the high speed mode of UART 1. 7 UART Speed SMSC DS – FDC37N769 Table 90 - CR0B FDD2 FDD1 DRT1 DRT0 DRT1 Table 91 - CR0C ...
Page 105
... CR0D CR0D can only be accessed in the configuration state and after the CSR has been initialized to 0DH. This register is read only. CR0D contains the FDC37N769 Device ID. The default value of this register after power up is 28H. CR0E CR0E can only be accessed in the configuration state and after the CSR has been initialized to 0EH. This register is read only ...
Page 106
... CR15 can only be accessed in the configuration state and after the CSR has been initialized to 15H. CR15 shadows the bits in the write-only UART1 run-time FCR register (Table 96). Table 96 - CR15: UART1 FCR Shadow Register D7 RCVR RCVR CR R TRIGGER TRIGGER 15 MSB SMSC DS – FDC37N769 Table 94 - CR11 BIT NAME DESCRIPTION Test 16 Test 17 Test 18 Test 19 RESERVED FOR SMSC USE Test 20 Test 21 Test 22 ...
Page 107
... CR1E is used to select the base address of the Game Chip Select decoder (GAMECS). The GAMECS can be set to 48 locations on 16 byte boundaries from 100H-3F0H. To disable the GAMECS, set DB1 and DB0 to zero (Table 100). DB7 DB6 ADR9 ADR8 SMSC DS – FDC37N769 DMA Reserved ...
Page 108
... FDC Address Decoding: nCS = ’0’ and A10 = ’0’ are required to access the FDC registers. A[3:0] are decoded as 0XXXb. Table 103 - CR20: FDC Base Address Register DB7 DB6 ADR9 ADR8 SMSC DS – FDC37N769 Table 100 - GAMECS Configuration Bits GAMECS CONFIGURATION DESCRIPTION DB1 DB0 ...
Page 109
... Serial Port 2 Address Decoding: nCS = ’0’ and A10 = ’0’ are required to access UART2 registers. A[2:0] are decoded as XXXb. Table 107 - CR25: UART2 Base Address Register DB7 DB6 ADR9 ADR8 SMSC DS – FDC37N769 DB5 DB4 DB3 ADR7 ADR6 ADR5 ADDRESSING (LOW BITS) DECODE ...
Page 110
... asserted 1 asserted 1 de-asserted 1 de-asserted asserted 1 de-asserted SMSC DS – FDC37N769 D3-D0 or D7-D4 DMA SELECTED 0000 None 0001 DMA_A 0010 DMA_B 0011 DMA_C D3-D0 or D7-D4 IRQ SELECTED 0000 None 0001 IRQ_A 0010 IRQ_B 0011 IRQ_C 0100 IRQ_D 0101 IRQ_E 0110 ...
Page 111
... ADR10, ADR9 and ADR8 to zero. SCE Address Decoding: nCS = ’0’ required to access SCE registers. A[2:0] are decoded as XXXb. Table 112 - CR2B: SCE (FIR) Base Address Register DB7 DB6 ADR10 ADR9 SMSC DS – FDC37N769 UART2 UART2 UART2 IRQ Share OUT2 bit Output State ...
Page 112
... CR2F can only be accessed in the configuration state and after the CSR has been initialized to 2FH. The default value of this register after power up is 00H (Table 116). CR2F is directly connected to SCE Register Block Three, Address 0x06 in the IRCC v2.0 block. D7 CR2F R/W SMSC DS – FDC37N769 D3-D0 DMA SELECTED 0000 None 0001 ...
Page 113
... Low Input Level High Input Level Input Leakage (All I and IS buffers except PWRGD) Low Input Leakage High Input Leakage Input Current PWRGD IO12 Type Buffer Low Output Level High Output Level Output Leakage SMSC DS – FDC37N769 SYMBOL MIN TYP MAX V 0.8 ILI V 2.0 IHI V 0.8 ...
Page 114
... Output Leakage OD14 Type Buffer Low Output Level Output Leakage OP14 Type Buffer Low Output Level High Output Level Output Leakage IOP14 Type Buffer Low Output Level High Output Level Output Leakage SMSC DS – FDC37N769 -10 +10 OL SYMBOL MIN ...
Page 115
... V A PARAMETER Clock Input Capacitance Input Capacitance Output Capacitance Table 119 - Capacitive Loading per Output Pin SIGNAL NAME SD[0:7] IOCHRDY IRQs DRQs nWGATE nWDATA nHDSEL nDIR nSTEP nDS[1:0] nMTR[1:0] SMSC DS – FDC37N769 SYMBOL MIN TYP MAX - ...
Page 116
... Data to Float Delay from nIOR High t6 Parallel Port Setup Read Strobe to Clear FINTR t7 t8 nIOR or nIOW Inactive for Transfers to and from ECP FIFO t9 nIOR Active to PINTR Inactive FIGURE 4 - MICROPROCESSOR READ TIMING SMSC DS – FDC37N769 TOTAL CAPACITANCE (pF) 240 100 100 100 240 240 240 240 240 ...
Page 117
... A0-A9, AEN, nIOCS16 Hold from nIOW High Data Set Up Time to nIOW High t4 t5 Data Hold Time from nIOW High t6 Write Strobe to Clear FINTR nIOW Inactive to PINTR Inactive t7 FIGURE 5 - MICROPROCESSOR WRITE TIMING SMSC DS – FDC37N769 t2 t4 DATA VALID min typ 40 150 ...
Page 118
... K H old A fter nIOW /nIO R H igh TC P ulse W idth t13 t14 nIO R /nIOW t15 from nDAC ctive active t16 SMSC DS – FDC37N769 t16 t14 t11 t6 t5 ...
Page 119
... Clock High Time/Low Time for 32KHz t2 Clock Rise Time/Fall Time (not shown) t4 nRESET Low Time The nRESET low time is dependent upon the processor clock. The nRESET must be active for a minimum of 24 x16MHz clock cycles. SMSC DS – FDC37N769 min 1.5 FIGURE 7 - CLOCK TIMING ...
Page 120
... DATA W rite Data W idth Low t9 nDS0-1, MTR0-1 from End of nIOW *X specifies one MCLK period and Y specifies one W CLK period. MCLK = 16x Data Rate (at 500 Kbp/s M CLK = 8 MHz) W CLK = 2x Data Rate (at 500 Kbp/s W CLK = 1 MHz) SMSC DS – FDC37N769 ...
Page 121
... IRQx Active Delay from nCTSx, nDSRx, nDCDx t3 IRQx Inactive Delay from nIOR (Leading Edge) t4 IRQx Inactive Delay from nIOW (Trailing Edge) t5 IRQx Inactive Delay from nIOW t6 IRQx Active Delay from nRIx SMSC DS – FDC37N769 Parameter min 10 FIGURE 9 - SERIAL PORT TIMING Page 121 of 137 DATASHEET t6 ...
Page 122
... Bit Time at 4.8kbaud t2 Bit Time at 2.4kbaud Notes: 1. Receive Pulse Detection Criteria: A received pulse is considered detected if the received pulse is a minimum of 1.41µs. 2. IRRX: CRC Bit RCV active low nIRRX: CRC Bit RCV active high (default) SMSC DS – FDC37N769 min 1.4 1 ...
Page 123
... Bit Time at 4.8kbaud t2 Bit Time at 2.4kbaud Notes: 1. IrDA @ 115k is HPSIR compatible. IrDA @ 2400 will allow compatibility with HP95LX and 48SX. 2. IRTX: CRC Bit XMIT active low (default) nIRTX: CRC Bit XMIT active high SMSC DS – FDC37N769 min 1.41 1 ...
Page 124
... Modulated Output "On" t6 Modulated Output "On" Notes: 1. IRRX: CRC Bit RCV active low nIRRX: CRC Bit RCV active high (default) MIRRX, nMIRRX are the modulated outputs FIGURE 12 - AMPLITUDE SHIFT KEYED IR RECEIVE TIMING SMSC DS – FDC37N769 min 0.8 ...
Page 125
... Modulated Output "On" t6 Modulated Output "On" Notes: 1. IRTX: CRC Bit XMIT active low (default) nIRTX: CRC Bit XMIT active high MIRTX, nMIRTX are the modulated outputs FIGURE 13 - AMPLITUDE SHIFT KEYED IR TRANSMIT TIMING SMSC DS – FDC37N769 min 0.8 ...
Page 126
... PINTR Active Low in ECP and EPP Modes PINTR Delay from nACK t4 nERROR Active to PINTR Active t5 PD0-PD7 Delay from nIOW Active t6 PINTR is the interrupt assigned to the Parallel Port SMSC DS – FDC37N769 Parameter min 200 FIGURE 14 - PARALLEL PORT TIMING Page 126 of 137 ...
Page 127
... Asserted to nWRITE Asserted NOTE: WAIT must be filtered to compensate for ringing on the parallel bus cable. WAIT is considered to have settled after it does not transition for a minimum of 50 nsec. FIGURE 15 - EPP 1.9 DATA OR ADDRESS WRITE CYCLE SMSC DS – FDC37N769 t10 t11 t16 t3 t14 ...
Page 128
... IOCHRDY t9 t21 nWRITE t2 t25 PD<7:0> DATASTB ADDRSTB nWAIT Timing parameter table for the EPP Data or Address Read Cycle is found on next page. FIGURE 16 - EPP 1.9 DATA OR ADDRESS READ CYCLE SMSC DS – FDC37N769 t13 t18 t10 PData bus driven t5 by peripheral t28 t1 t14 t15 t7 Page 128 of 137 ...
Page 129
... NOTES WAIT is considered to have settled after it does not transition for a minimum of 50 ns. 2. When not executing a write cycle, EPP nWRITE is inactive high true only FIGURE 17 - EPP 1.9 DATA OR ADDRESS READ CYCLE TIMING PARAMETERS SMSC DS – FDC37N769 Parameter min ...
Page 130
... Command Deasserted to nWAIT Deasserted NOTES: 1. WRITE is controlled by clearing the PDIR bit to "0" in the control register before performing an EPP W rite. 2. This number is only valid if WAIT is active when nIOW goes active. FIGURE 18 - EPP 1.7 DATA OR ADDRESS WRITE CYCLE SMSC DS – FDC37N769 t6 t10 t20 t13 t1 ...
Page 131
... Deasserted to nIOW or nIOR Asserted t22 nIOR Asserted to Command Asserted t23 NOTE: 1. nWRITE is controlled by setting the PDIR bit to "1" in the control register before performing an EPP Read. FIGURE 19 - EPP 1.7 DATA OR ADDRESS READ CYCLE SMSC DS – FDC37N769 t15 t13 t3 t10 t5 Parameter min ...
Page 132
... HostAck (nAutoFd) high to acknowledge the handshake. The peripheral then sets PeriphClk (nAck) high. After the host has accepted the data it sets HostAck (nAutoFd) low, completing the transfer. This sequence is shown in 21 FIGURE . SMSC DS – FDC37N769 Page 132 of 137 DATASHEET Rev. 02-16-07 ...
Page 133
... BUSY Inactive to nSTROBE Active t6 BUSY Inactive to PDATE Invalid NOTE: 1. The data is held until BUSY goes inactive or for time t3, whichever is longer. This only applies if another data transfer is pending other data transfer is pending, the data is held indefinitely. SMSC DS – FDC37N769 Parameter min 600 ...
Page 134
... Asserted to nSTROBE Deasserted NOTES: 1. Maximum value only applies if there is data in the FIFO waiting to be written out. 2. BUSY is not considered asserted or deasserted until it is stable for a minimum 130 ns. FIGURE 21 - ECP PARALLEL PORT FORWARD TIMING SMSC DS – FDC37N769 ...
Page 135
... Maximum value only applies if there is room in the FIFO and a terminal count has not been received. ECP can stall by keeping nAUTOFD low. 2. nACK is not considered asserted or deasserted until it is stable for a minimum 130 ns. FIGURE 22 - ECP PARALLEL PORT REVERSE TIMING SMSC DS – FDC37N769 ...
Page 136
... Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25mm per side. 4 Dimension for foot length L are measured at the gauge plane 0.25mm above the seating plane. 5 Details of pin 1 identifier are optional but must be located within the zone indicated. 6. Controlling dimension: millimeter FIGURE 23 - 100 PIN TQFP PACKAGE OUTLINE SMSC DS – FDC37N769 D1/4 E1/4 ...
Page 137
... REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. SMSC DS – FDC37N769 Page 137 of 137 DATASHEET Rev. 02-16-07 ...