LH75401_LH75411_N NXP Semiconductors, LH75401_LH75411_N Datasheet - Page 54
LH75401_LH75411_N
Manufacturer Part Number
LH75401_LH75411_N
Description
The NXP BlueStreak LH75401/LH75411 family consists of two low-cost 16/32-bit System-on-Chip (SoC) devices
Manufacturer
NXP Semiconductors
Datasheet
1.LH75401_LH75411_N.pdf
(63 pages)
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LH75401/LH75411
54
NOTE: LCDDCLK can range from 4.5 MHz to 6.8 MHz.
NOTE:
*
SYNCHRONIZATION)
*
(INTERNAL)
APBPeriphClkCtrl1:LCD
ClkPrescale:LCDPS
(SHOWN FOR REFERENCE)
Source is RCPC.
SYNCHRONIZATION
(LCD VIDEO DATA)
CLCDCLK
(HORIZONTAL
(VERTICAL
LCDVD[11:0]
LCDSPS
LCDSPL
(AD-TFT, HR-TFT
START PULSE LEFT)
LCDLP
(HORIZONTAL
SYNCHRONIZATION
PULSE)
LCDLP
(HORIZONTAL
SYNCHRONIZATION
PULSE)
PULSE)
LCDLP
LCDDCLK
(DELAYED FOR
AD-TFT, HR-TFT)
LCDVD[11:0]
(DELAYED FOR
AD-TFT, HR-TFT)
LCDDCLK
(PANEL CLOCK)
Timing2:PCD
Timing2:BCD
Timing2:IPC
Timing2:CPL
LCDEN
(DATA ENABLE)
LCDVD[11:0]
LCDCLS
LCDREV
LCDPS
Figure 19. AD-TFT, HR-TFT Horizontal Timing Diagram
Figure 20. AD-TFT, HR-TFT Vertical Timing Diagram
AD-TFT and HR-TFT SIGNALS ARE TFT SIGNALS, RE-TIMED
1.5 µs - 4 µs
Timing0:HSW
Timing1:VSW
Timing1:CLSDEL
Timing1:LPDEL
Timing0:HSW +
Timing0: HBP
NXP Semiconductors
Rev. 01 — 16 July 2007
1 LCDDCLK
1 LCDDCLK
001
002 003 004 005 006 007 008
1 AD-TFT or HR-TFT HORIZONTAL LINE
001
002 003 004 005 006
Timing2:CLSDEL2
PIXEL DATA
Timing1:REVDEL
320
317
318
319 320
Preliminary data sheet
System-on-Chip
LH754xx-80
LH754xx-81
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