CY7C4285V-10ASC Cypress Semiconductor Corp, CY7C4285V-10ASC Datasheet

IC DEEP SYN FIFO 64KX18 64LQFP

CY7C4285V-10ASC

Manufacturer Part Number
CY7C4285V-10ASC
Description
IC DEEP SYN FIFO 64KX18 64LQFP
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Datasheet

Specifications of CY7C4285V-10ASC

Function
Synchronous
Memory Size
1.1K (64 x 18)
Data Rate
100MHz
Access Time
8ns
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1242
Cypress Semiconductor Corporation
Document #: 38-06012 Rev. *A
Features
• 3.3V operation for low power consumption and easy
• High-speed, low-power, first-in first-out (FIFO)
• 8K x 18 (CY7C4255V)
• 16K x 18 (CY7C4265V)
• 32K x 18 (CY7C4275V)
• 64K x 18 (CY7C4285V)
• 0.35 micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10-ns read/write cycle
• Low power
• Fully asynchronous and simultaneous read and write
• Empty, Full, Half Full, and programmable Almost Empty
• Retransmit function
• Output Enable (OE) pin
• Independent read and write enable pins
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
• Depth Expansion Capability
• 64-pin 10x10 STQFP
• Pin-compatible density upgrade to CY7C42X5V-ASC
• Pin-compatible 3.3V solutions for CY7C4255/65/75/85
Logic Block Diagram
integration into low-voltage systems
memories
times)
operation
and Almost Full status flags
families
— I
— I
CC
SB
= 4 mA
= 30 mA
WXO/HF
FL/RT
RXO
WXI
RXI
RS
WCLK
EXPANSION
CONTROL
POINTER
RESET
WRITE
WRITE
LOGIC
LOGIC
32K/64Kx18 Low Voltage Deep Sync FIFOs
WEN
3901 North First Street
OUTPUT REGISTER
THREE-ST ATE
REGISTER
High
Density
Dual-Port
RAM Array
D
Q
16Kx9
32Kx9
64Kx9
INPUT
0 – 17
8Kx9
0 – 17
Functional Description
The CY7C4255/65/75/85V are high-speed, low-power, first-in
first-out (FIFO) memories with clocked read and write interfac-
es. All are 18 bits wide and are pin/functionally compatible to
the
CY7C4255/65/75/85V can be cascaded to increase FIFO
depth. Programmable features include Almost Full/Almost
Empty flags. These FIFOs provide solutions for a wide variety of
data buffering needs, including high-speed data acquisition, multipro-
cessor interfaces, and communications buffering.
These FIFOs have 18-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (WCLK) and a write enable
pin (WEN).
When WEN is asserted, data is written into the FIFO on the rising
edge of the WCLK signal. While WEN is held active, data is continu-
ally written into the FIFO on each cycle. The output port is controlled
in a similar manner by a free-running read clock (RCLK) and a read
enable pin (REN). In addition, the CY7C4255/65/75/85V have an
output enable pin (OE). The read and write clocks may be tied togeth-
er for single-clock operation or the two clocks may be run indepen-
dently for asynchronous read/write applications. Clock frequencies
up to 67 MHz are achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the cascade input (WXI,
RXI), cascade output (WXO, RXO), and First Load (FL) pins. The
WXO and RXO pins are connected to the WXI and RXI pins of the
next device, and the WXO and RXO pins of the last device should be
connected to the WXI and RXI pins of the first device. The FL pin of
the first device is tied to V
es should be tied to V
OE
CY7C42X5V
RCLK
San Jose
PROGRAM
REGISTER
CONTROL
POINTER
FLAG
LOGIC
FLAG
READ
READ
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
REN
CC
.
SS
Synchronous
4275V–1
and the FL pin of all the remaining devic-
FF
EF
PAE
PAF
SMODE
CA 95134
Revised December 26, 2002
FIFO
408-943-2600
family.
The

Related parts for CY7C4285V-10ASC

CY7C4285V-10ASC Summary of contents

Page 1

... High-speed, low-power, first-in first-out (FIFO) memories • (CY7C4255V) • 16K x 18 (CY7C4265V) • 32K x 18 (CY7C4275V) • 64K x 18 (CY7C4285V) • 0.35 micron CMOS for optimum speed/power • High-speed 100-MHz operation (10-ns read/write cycle times) • Low power — I ...

Page 2

... CY7C4265V 16K x 18 64-pin 10x10 TQFP CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V GND GND GND 4275V–3 /SMODE is tied 7C4255/65/75/85V-15 7C4255/65/75/85V-25 66 CY7C4275V CY7C4285V 32K x 18 64K x 18 64-pin 10x10 TQFP 64-pin 10x10 TQFP . All Page ...

Page 3

... HIGH, the FIFO’s outputs are in High Z (high-impedance) state. I Dual-Mode Pin: Asynchronous Almost Empty/Almost Full flags – tied to V Synchronous Almost Empty/Almost Full flags – tied to V (Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.) CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V Function /SMODE is tied CC /SMODE is tied /SMODE is tied to ...

Page 4

... IH < V < Com’l Ind Com’l Ind Test Conditions T = 25° MHz 3.3V CC CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V Ambient Temperature 0°C to +70°C 3.3V ±300 mV [2] –40°C to +85°C 3.3V ±300 mV 7C4255/65/75/ 7C4255/65/75/ 85V-15 85V-25 Min. Max. Min. 2.4 2.4 0.4 2 ...

Page 5

... Equivalent to: THÉ VENIN EQUIVALENT OUTPUT 3.0V 50 GND 4275V–6 7C4255/65/75/85V -10 Min. Max. 100 4.5 4.5 3 [12 OHZ CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V ALL INPUT PULSES 90% 90% 10% 10 200 2.0V ALL INPUT PULSES 90% 90% 10% 10 7C4255/65/75/85V 7C4255/65/75/85V -15 -25 Min. Max. Min. 66 ...

Page 6

... Empty and Programmable Almost Full Flags (Synchronous Mode only) Note: 13 after program register write will not be valid until PAFasynch PAEasynch Document #: 38-06012 Rev. *A 7C4255/65/75/85V -10 Min. Max. [12 /SMODE tied /SMODE CC 8 /SMODE tied 4 PAF(E) CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V 7C4255/65/75/85V 7C4255/65/75/85V -15 -25 Min. Max. Min. Max 6 Page ...

Page 7

... NO OPERATION t REF [15] t SKEW2 , then FF may not change state until the next WCLK rising edge. SKEW1 , then EF may not change state until the next RCLK rising edge. SKEW2 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V ENH NO OPERATION t WFF t REF VALID DATA t OHZ 4275V–8 4275V–9 ...

Page 8

... The first word is always available the cycle after EF goes HIGH. Document #: 38-06012 Rev RSF t RSF t RSF D 1 [18] t FRL t SKEW2 t REF t OLZ t OE (maximum When t FRL CLK SKEW2 SKEW2 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V t RSR OE=1 OE [19 < minimum specification, t (maximum) = either 2*t FRL [17] 4275V– 4275V– CLK SKEW2 Page ...

Page 9

... ENS REN LOW OE DATA IN OUTPUT REGISTER Q – Document #: 38-06012 Rev. *A [18 REF REF DATA WRITE t WFF t ENH t A DATA READ CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V ENH ENS [18] t FRL t t SKEW2 D0 NO WRITE [14] t SKEW1 t t WFF WFF t ENH t ENS t A NEXT DATA READ REF 4275V– ...

Page 10

... PAE is offset = n. Number of data words into FIFO already = n. Document #: 38-06012 Rev CLKL CLKH t t ENS ENH CLKL CLKH t t ENS ENH t PAE CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V HALF FULL + 1 OR MORE HALF FULL OR LESS ENS WORDS n WORDS IN FIFO IN FIFO t PAE t ENS 4275V–14 4275V–15 Page ...

Page 11

... PAF offset = m. Number of data words written into FIFO already = 8192 1) for the CY7C4275V, and 65536 ( for the CY7C4285V. 25. PAF is offset = m. 26. 8192 m words in CY7C4255V, 16384 27. 8192 ( words in CY7C4255V, 16384 ( words in CY7C4265V, 32768 ( words in CY7C4275V, and 65536 ( words in CY7C4285V. Document #: 38-06012 Rev CLKL t t ...

Page 12

... IN FIFO t CLKL t ENH t DH PAE OFFSET PAF OFFSET (m 1) words of the FIFO when PAF goes LOW. , then PAF may not change state until the next WCLK rising edge. SKEW3 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V FULL– M WORDS [26] IN FIFO t [29] PAF synch t SKEW3 ENS ...

Page 13

... WCLK Notes: 30. Write to Last Physical Location. 31. Read from Last Physical Location. Document #: 38-06012 Rev CLKL t ENH t A UNKNOWN PAE OFFSET t CLKH Note Note CLKH Note XIS CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V PAF OFFSET PAE OFFSET 4275V–20 4275V–21 4275V–22 4275V–23 Page ...

Page 14

... Clocks are free-running in this case. 33. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at t 34. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after t Document #: 38-06012 Rev. *A CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V XIS ...

Page 15

... Empty. See Table 2 for a description of programmable flags. When the SMODE pin is tied LOW, the PAF flag signal transi- tion is caused by the rising edge of the write clock and the PAE flag transition is caused by the rising edge of the read clock. CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V [35] WCLK Selection Writing to offset registers: ...

Page 16

... FIFO that is “staggered” by one clock cycle due to the variations in skew between RCLK and WCLK. Figure 1 demonstrates a 36-word width by using two CY7C4255/65/75/85Vs. RESET (RS) 18 7C4255V 7C4265V 7C4275V 7C4285V FIRST LOAD (FL) WRITE EXPANSION IN (WXI) READ EXPANSION IN (RXI) Configuration CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V [36 ...

Page 17

... WXI RXI WXO RXO 7C4255V 7C4265V 7C4275V 7C4285V PAF PAE WXI RXI WXO RXO 7C4255V 7C4265V 7C4275V 7C4285V FF EF PAE PAF WXI RXI FIRST LOAD (FL) CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V DATA OUT (Q) READ CLOCK (RCLK) READ ENABLE (REN) OUTPUT ENABLE (OE) EF PAE 4275V–25 Page ...

Page 18

... Thin Quad Flatpack Package Package Name Type A64 64-Lead 10x10 Thin Quad Flatpack A64 64-Lead 10x10 Thin Quad Flatpack A64 64-Lead 10x10 Thin Quad Flatpack CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V Operating Range Commercial Commercial Commercial Operating Range Commercial Commercial Commercial Operating Range ...

Page 19

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V 51-85051-A Page ...

Page 20

... Document Title: CY7C4255V, CY7C4265V, CY7C4275V, CY7C4285V 32K/64K x 18 Low Voltage Deep Sync FIFOs Document Number: 38-06012 Issue REV. ECN NO. Date ** 106473 09/10/01 *A 122264 12/26/02 Document #: 38-06012 Rev. *A Orig. of Change SZV Change from Spec number: 38-00654 to 38-06012 RBI Power up requirements added to Maximum Ratings Information ...

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