CY7C4261-15JXCT Cypress Semiconductor Corp, CY7C4261-15JXCT Datasheet - Page 4

• Manufacturer Part Number: CY7C4261-15JXCT
• Description: IC SYNC FIFO MEM 16KX9 32-PLCC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4261-15JXCT

• Function: Synchronous
• Memory Size: 144K (16K x 9)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
The CY7C4261/71 provides four status pins: Empty, Full,
Programmable Almost Empty, and Programmable Almost Full.
The Almost Empty/Almost Full flags are programmable to single
word granularity. The programmable flags default to Empty + 7
and Full – 7.
The flags are synchronous, that is, they change state relative to
either the read clock (RCLK) or the write clock (WCLK). When
entering or exiting the Empty and Almost Empty states, the flags
are updated exclusively by the RCLK. The flags denoting Almost
Full, and Full states are updated exclusively by WCLK. The
synchronous flag architecture guarantees that the flags maintain
their status for at least one cycle.
All configurations are fabricated using an advanced 0.5μ CMOS
technology. Input ESD protection is greater than 2001V, and
latch-up is prevented by the use of guard rings.
Architecture
The CY7C4261/71 consists of an array of 16K to 32K words of
nine bits each (implemented by a dual port array of SRAM cells),
a read pointer, a write pointer, control signals (RCLK, WCLK,
REN1, REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF, FF).
Resetting the FIFO
Upon power up, the FIFO must be reset with a Reset (RS) cycle.
This causes the FIFO to enter the Empty condition signified by
EF being LOW. All data outputs (Q
rising edge of RS. For the FIFO to reset to its default state, a
falling edge must occur on RS and the user must not read or write
while RS is LOW. All flags are guaranteed to be valid t
RS is taken LOW.
FIFO Operation
When the WEN1 signal is active LOW, WEN2 is active HIGH,
and FF is active HIGH, data present on the D
into the FIFO on each rising edge of the WCLK signal. Similarly,
when the REN1 and REN2 signals are active LOW and EF is
active HIGH, data in the FIFO memory is presented on the Q
outputs. New data is presented on each rising edge of RCLK
while REN1 and REN2 are active. REN1 and REN2 must set up
t
WEN2 must occur t
function.
An output enable (OE) pin is provided to three-state the Q
outputs when OE is asserted. When OE is enabled (LOW), data
in the output register is available to the Q
devices are cascaded, the OE function only outputs data on the
FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional writes
when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q
after additional reads occur.
Document #: 38-06015 Rev. *D
ENS
before RCLK for it to be a valid read function. WEN1 and
ENS
before WCLK for it to be a valid write
0−8
) go LOW t
0−8
outputs after t
0−8
0−8
pins is written
RSF
outputs even
RSF
after the
OE
after
0−8
0−8
. If
Write Enable 1 (WEN1). If the FIFO is configured for
programmable flags, Write Enable 1 (WEN1) is the only write
enable control pin. In this configuration, when Write Enable 1
(WEN1) is LOW, data can be loaded into the input register and
RAM array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored is the RAM array sequentially and
independently of any on-going read operation.
Write Enable 2/Load (WEN2/LD). This is a dual purpose pin.
The FIFO is configured at Reset to have programmable flags or
to have two write enables, which allows for depth expansion. If
Write Enable 2/Load (WEN2/LD) is set active HIGH at Reset (RS
= LOW), this pin operates as a second write enable pin.
If the FIFO is configured to have two write enables, when Write
Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/LD) is
HIGH, data can be loaded into the input register and RAM array
on the LOW-to-HIGH transition of every write clock (WCLK).
Data is stored in the RAM array sequentially and independently
of any ongoing read operation.
Programming
When WEN2/LD is held LOW during Reset, this pin is the load
(LD) enable for flag offset programming. In this configuration,
WEN2/LD can be used to access the four 8-bit offset registers
contained in the CY7C4261/71 for writing or reading data to
these registers.
When the device is configured for programmable flags and both
WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH transition
of WCLK writes data from the data inputs to the empty offset least
significant bit (LSB) register. The second, third, and fourth
LOW-to-HIGH transitions of WCLK store data in the empty offset
most significant bit (MSB) register, full offset LSB register, and
full offset MSB register, respectively, when WEN2/LD and WEN1
are LOW. The fifth LOW-to-HIGH transition of WCLK while
WEN2/LD and WEN1 are LOW writes data to the empty LSB
register again.
values for the various device types.
Figure 3. Offset Register Location and Default Values
8
8
8
8
Empty Offset (LSB) Reg.
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
7
7
16K × 9
5
5
Figure 3
000000
(MSB)
000000
(MSB)
shows the register sizes and default
CY7C4261, CY7C4261
0
0
0
0
8
8
8
8
Empty Offset (LSB) Reg.
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
7
7
32K × 9
6
6
0000000
0000000
(MSB)
(MSB)
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