lm2501sl National Semiconductor Corporation, lm2501sl Datasheet
lm2501sl
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lm2501sl Summary of contents
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... MPL interface. When PD* is asserted, the MD, MC and WC signals are powered down to save current and reduce power dissipation. Typical Application Diagram Ordering Information NSID LM2501SL I2C is a registered trademark of Phillips Corporation. ® © 2004 National Semiconductor Corporation Features n 160 Mbps Raw Throughput ...
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Connection Diagram General Block Diagrams: Serializer and Deserializer www.national.com TOP VIEW 2 20091612 20091613 ...
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Pin Description No. Pin Name I/O, Type of Pins MPL SERIAL BUS PINS MD 1 IO, MPL MC 1 IO, MPL MG 1 Ground CONFIGURATION/PARALLEL BUS PINS Mode[1: LVCMOS PD LVCMOS D0–D7 8 IO, LVCMOS VS ...
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Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V ) DDA Supply Voltage ( Supply Voltage (V ) DDIO LVCMOS Input/Output Voltage MPL ...
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Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2) Symbol Parameter PARALLEL BUS TIMING t Set Time - Data to Clock SET t Hold Time - Clock to Data HOLD t Rise Time RISE t ...
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Input Timing Requirements Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2) Symbol Parameter REFERENCE CLOCK (WCLK ) IN f Clock Frequency WC WC Clock Duty Cycle DC t Clock Transition Times T (Rise or Fall, 10%–90%) ...
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Application Information Typical application connections for the LM2501 are shown below. The application shown in Figure 3 illustrates a connection between an Image sensor and a host utilizing an MPL-0 link. . FIGURE 3. Camera Application 7 20091614 www.national.com ...
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Functional Description SERIAL BUS OPERATION Bus Overview The MPL bus is a simple 2-signal line interface that is intended to replace wide low voltage CMOS video busses inside handheld portable devices. The MPL physical layer is purpose-built for an extremely ...
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Functional Description SERIAL BUS POWER-UP In the sleep state, WC, MC and MD are turned off with zero current flowing. Both devices need to be enabled by assert- ing their PD* inputs. The DES will then initialize the SER via ...
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Functional Description In Figure 6 , the Serializer timing is shown. For the part to establish lock, WCLKIO(out) must be active, and a valid PCLK applied. After lock is obtained, the MC and MD lines are initialized and then active ...
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Functional Description CAMERA INTERFACE The Camera Interface provides serialization of color and control bits. The interface provides data transport in a single direction. Byte alignment is provided by the intrinsic first rising edge of the MC line. PCLK is required ...
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Features and Operation POWER DOWN/OFF The device may be powered by its PD* pin. A Low on this pin will power down the entire device. TABLE 2. Power Down Output States Mode Pin Type SER WCLKIO LVCMOS SER MC MPL ...
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Features and Operation When the Deserializer’s PD* signal is de-asserted, the WC output will power up and initialize the serializer and start transmitting the clock reference. Once the Serializer re- ceived the clock, it waits seven cycles, and then outputs ...
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... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. inches (millimeters) unless otherwise noted Order Number LM2501SL NS Package Number SLE24A 2 ...