at17lv010-10dp ATMEL Corporation, at17lv010-10dp Datasheet
at17lv010-10dp
Related parts for at17lv010-10dp
at17lv010-10dp Summary of contents
Page 1
... Available in 400 mils Wide 28 Pins DIL Flat Pack Description The AT17LV010-10DP is a FPGA Configuration Serial EEPROM provides an easy-to- use, cost-effective configuration memory for Field Programmable Gate Arrays packaged in the 28-pin 400 mils wide FP package. Configurator uses a simple serial- access procedure to configure one or more FPGA devices. The user can select the polarity of the reset function by programming four EEPROM bytes ...
Page 2
... Pin Configuration AT17LV010-10DP 2 Figure 1. 28-pin Flat Pack RESET/OE NC WP2 CE GND CE0(A2 READY Note: * indicates this pin must not be used NC WP1 25 4 CLK 24 5 DATA VCC SER_EN ...
Page 3
... DATA output pin and enable the address counter. When RESET/OE is driven High, the configuration EEPROM resets its address counter and tri-states its DATA pin. The CE pin also controls the output of the AT17LV010-10DP configurator held High after the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri- stated ...
Page 4
... Ground pin. A 0.2 µF decoupling capacitor between V Chip Enable Output (active Low). This output goes Low when the address counter has reached its maximum value daisy chain of AT17LV010-10DP devices, the CEO pin of one device must be connected to the CE input of the next device in the chain. It will stay Low as long Low and OE is High. It will then follow CE until OE goes Low ...
Page 5
... The master FPGA CCLK output drives the CLK input of the AT17LV010-10DP configurator. • The CEO output of any AT17LV010-10DP configurator drives the CE input of the next configurator in a cascaded chain of EEPROMs. • SER_EN must be connected to V • The READY pin is available as an open-collector indicator of the device’s reset status ...
Page 6
... This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under oper- ating conditions is not implied. Exposure to Abso- lute Maximum Rating conditions for extended periods of time may affect device reliability. 3.3V Min Max 3.0 3.6 AT17LV010-10DP Min 2 mA ...
Page 7
... AC Characteristics CE RESET/OE CLK T CE DATA AC Characteristics when Cascading RESET/OE CE CLK T DATA T CEO 4265C–AERO–05/05 T SCE CAC CDF LAST BIT T OCK OCE AT17LV010-10DP T SCE T T HOE FIRST BIT T OOE T OCE HCE 7 ...
Page 8
... AC Characteristics AC Characteristics when Cascading AT17LV010-10DP 3.3V ± 0.3V CC Symbol Description ( Data Delay OE ( Data Delay CE (1) T CLK to Data Delay CAC T Data Hold from CE, OE, or CLK OH ( Data Float Delay DF T CLK Low Time LC T CLK High Time ...
Page 9
... Ordering Information Memory Size 1 Mbit 1 Mbit AT17LV010-10DP-MQ 1 Mbit AT17LV010-10DP-SV 4265C–AERO–05/05 Ordering Code AT17LV010-10DP-E AT17LV010-10DP Package Operation Range 28-pin Flat Pack Engineering Samples 28-pin Flat Pack Military Level B 28-pin Flat Pack Space Level B 9 ...
Page 10
... Packaging Information DP (FP28.4) AT17LV010-10DP 10 4265C–AERO–05/05 ...
Page 11
... Atmel Corporation 2005. All rights reserved. Atmel ® marks, and Everywhere You Are are the trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory ...