at17n040 ATMEL Corporation, at17n040 Datasheet

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at17n040

Manufacturer Part Number
at17n040
Description
At17n512 512k-bit Fpga Configuration Eeprom 3.3v
Manufacturer
ATMEL Corporation
Datasheet

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at17n040-10TQC
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at17n040-10TQI
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Quantity:
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Features
Description
The AT17N series FPGA Configuration EEPROM (Configurators) provide an easy-to-
use, cost-effective configuration memory for Field Programmable Gate Arrays. The
AT17N series device is packaged in the 8-lead PDIP, 8-lead SOIC, 20-lead SOIC and
44-lead TQFP, see Table 1. The AT17N series Configurators uses a simple serial-
access procedure to configure one or more FPGA devices.
The AT17N series configurators can be programmed with industry-standard program-
mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable and
factory programming.
Table 1. AT17N Series Packages
Package
8-lead PDIP
8-lead SOIC
20-lead SOIC
44-lead TQFP
EE Programmable 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-, 2,097,152 x 1-, and
4,194,304 x 1-bit Serial Memories Designed to Store Configuration Programs for Field
Programmable Gate Arrays (FPGAs)
Available as a 3.3V (±10%) Commercial and Industrial Version
Simple Interface to SRAM FPGAs
Pin Compatible with Xilinx
Compatible with Xilinx Spartan
Mode
Very Low-power CMOS EEPROM Process
Available in 8-lead PDIP, 8-lead SOIC, 20-lead SOIC and 44-lead TQFP Packages for a
Specific Density
Low-power Standby Mode
High-reliability
– Endurance: Minimum 10 Write Cycles
– Data Retention: 20 Years at 85°C
AT17N256
Yes
Yes
Yes
®
XC17SXXXA and XC17SXXXXL PROMs
®
-II, Spartan-IIE and Spartan XL FPGAs in Master Serial
AT17N512/
AT17N010
Yes
Yes
AT17N002
Yes
Yes
AT17N040
Yes
FPGA
Configuration
Memory
AT17N256
AT17N512
AT17N010
AT17N002
AT17N040
3.3V
System Support
3020C–CNFG–08/07
1

Related parts for at17n040

at17n040 Summary of contents

Page 1

... PDIP Yes 8-lead SOIC Yes 20-lead SOIC Yes 44-lead TQFP – AT17N512/ AT17N010 AT17N002 Yes – – – Yes Yes – Yes FPGA Configuration Memory AT17N256 AT17N512 AT17N010 AT17N002 AT17N040 3.3V AT17N040 System Support – – – Yes 3020C–CNFG–08/07 1 ...

Page 2

Pin Configuration AT17N256/512/010/002/040 2 8-lead SOIC DATA 1 8 VCC CLK 2 7 VCC (SER_EN) RESET/ GND 8-lead PDIP DATA 1 8 VCC CLK 2 7 VCC (SER_EN) RESET/ ...

Page 3

AT17N256/512/010/002/040 44 TQFP ...

Page 4

Block Diagram SER_EN POWER ON RESET Device Description AT17N256/512/010/002/040 4 The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) inter- face directly with the FPGA device control signals. All FPGA devices can control the entire configuration process and ...

Page 5

... DC pins are No Connect pins internally connected to the die not recommended to connect these pins to any external signal. AT17N256/512/010/002/040 AT17N002 SOIC SOIC TQFP – – and GND is recommended. CC AT17N040 44 TQFP ...

Page 6

FPGA Master Serial Mode Summary Control of Configuration Programming Mode Standby Mode AT17N256/512/010/002/040 6 The I/O and logic functions of any SRAM-based FPGA are established by a configura- tion program. The program is loaded either automatically upon power-up ...

Page 7

Absolute Maximum Ratings* Operating Temperature.................................... -40°C to +85 °C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground ..............................-0. Supply Voltage (V ) .......................................... 3.0V to +3.6V CC Maximum Soldering Temp. (10 sec. ...

Page 8

... Industrial 100 AT17N256 Commercial Industrial Min Max Min Max AT17N002/ AT17N010 AT17N040 Max Min Max Units V 2 0.8 0 0.8 2.4 0.4 0.4 2.4 0.4 0 -10 10 100 150 100 150 AT17N512/010/002/040 Commercial Industrial Min ...

Page 9

AC Characteristics CE RESET/OE CLK T CE DATA 3020C–CNFG–08/07 T SCE CAC AT17N256/512/010/002/040 T SCE T HOE HCE 9 ...

Page 10

... JC θ 150 JA (2) [°C/W] θ [°C/W] JC θ JA (2) [°C/W] θ [°C/W] – JC θ – JA (2) [°C/W] AT17N002 AT17N040 37 – 107 – – – – – – 17 – 62 3020C–CNFG–08/07 – – – – – – ...

Page 11

Figure 1. Ordering Code Voltage 3.3V 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 20S2 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 44A 44-lead, Thin ...

Page 12

... Ordering Code AT17N256-10PC AT17N256-10NC AT17N256-10SC AT17N256-10PI AT17N256-10NI AT17N256-10SI AT17N512-10SC AT17N512-10SI AT17N010-10SC AT17N010-10SI AT17N002-10SC AT17N002-10TQC AT17N002-10SI AT17N002-10TQI AT17N040-10TQC AT17N040-10TQI Package Operation Range 8P3 Commercial 8S1 (0°C to 70°C) 20S2 8P3 Industrial 8S1 (-40°C to 85°C) 20S2 Commercial 20S2 (0°C to 70°C) Industrial 20S2 (-40° ...

Page 13

Packaging Information 8P3 – PDIP Top View PLCS Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured ...

Page 14

SOIC TOP VIEW e e SIDE VIEW Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R ...

Page 15

SOIC 3020C–CNFG–08/07 AT17N256/512/010/002/040 15 ...

Page 16

TQFP PIN 1 PIN 1 IDENTIFIER e C 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. ...

Page 17

Revision History Revision Level – Release Date B – March 2006 C – August 2007 3020C–CNFG–08/07 AT17N256/512/010/002/040 History Added last-time buy for AT17NXXX-10CC and AT17NXXX-10CI. Removed 8CN4 8-lead LAP package. 17 ...

Page 18

... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © Atmel Corporation 2007. All rights reserved. Atmel marks or trademarks of Atmel Corporation or its subsidiaries. FLEX ® Semiconductors; SPARTAN and Virtex ™ ...

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