EPF10K100 ALTERA [Altera Corporation], EPF10K100 Datasheet - Page 43

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EPF10K100

Manufacturer Part Number
EPF10K100
Description
Embedded Programmable Logic Device Family
Manufacturer
ALTERA [Altera Corporation]
Datasheet

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Figure 18
Figure 18. JTAG Waveforms
Captured
Table 16
Symbol
Table 16. JTAG Timing Parameters & Values
t
t
t
t
t
t
t
t
t
t
t
t
t
Driven
Signal
Signal
JCP
JCH
JCL
JPSU
JPH
JPCO
JPZX
JPXZ
JSSU
JSH
JSCO
JSZX
JSXZ
to Be
to Be
TMS
TDO
TCK
TDI
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
shows the timing parameters and values for FLEX 10K devices.
TCK clock period
TCK clock high time
TCK clock low time
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high-impedance to valid output
Update register valid output to high impedance
shows the timing requirements for the JTAG signals.
t
JCH
t
t
JPZX
JSZX
t
JCP
t
JSSU
t
JCL
Parameter
t
JSH
t
t
JPCO
JSCO
t
JPSU
t
t
JSXZ
JPH
Min
100
50
50
20
45
20
45
t
JPXZ
Max
25
25
25
35
35
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
43

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