MAX2309EGI Maxim Integrated, MAX2309EGI Datasheet
MAX2309EGI
Specifications of MAX2309EGI
Related parts for MAX2309EGI
MAX2309EGI Summary of contents
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... Programmable Interface ♦ Low Supply Voltage (+2.7V) PART MAX2306EGI MAX2306ETI MAX2308EGI Applications MAX2308ETI MAX2309EGI MAX2309ETI *Exposed paddle Pin Configurations appear at end of data sheet. Block Diagram appears at end of data sheet. MODE DESCRIPTION AMPS, Dual Band, Triple Mode with Two IF VCOs ...
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer ABSOLUTE MAXIMUM RATINGS V to GND ...........................................................-0.3V to +6.0V CC SHDN to GND.............................................-0. STBY, BUFEN, MODE, EN, DATA, CLK, DIVSEL ...........................................-0. VGC to GND...............-0.3V, the lesser ...
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CDMA IF VGAs and I/Q Demodulators AC ELECTRICAL CHARACTERISTICS (MAX2306/MAX2308/MAX2309 EV kit 19.2MHz, 0.6Vp-p synthesizer locked with passive 3rd-order lead-lag loop filter, SHDN = high, VGC set for f = 183.7MHz REF +35dB voltage gain, differential ...
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer AC ELECTRICAL CHARACTERISTICS (continued) (MAX2306/MAX2308/MAX2309 EV kit 19.2MHz, 0.6Vp-p synthesizer locked with passive 3rd-order lead-lag loop filter, SHDN = high, VGC set for f = 183.7MHz, f ...
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CDMA IF VGAs and I/Q Demodulators (MAX2306/MAX2308/MAX2309 EV kits, V synthesizer locked with passive 3rd-order lead-lag loop filter, SHDN = high, VGC set for +35dB voltage gain, differential output load = 10kΩ, all power levels referred to 50Ω, T RECEIVE ...
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer (MAX2306/MAX2308/MAX2309 EV kits, V synthesizer locked with passive 3rd-order lead-lag loop filter, SHDN = high, VGC set for +35dB voltage gain, differential output load = 10kΩ, all power levels referred ...
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CDMA IF VGAs and I/Q Demodulators PIN MAX2306 MAX2308 MAX2309 1, 28 — — — — — — — — — — ...
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer PIN MAX2306 MAX2308 MAX2309 — — — 28 Exposed Paddle _______________Detailed Description The MAX2306 is intended for dual-band (PCS ...
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CDMA IF VGAs and I/Q Demodulators 2.4kΩ 0.068µF 33pF 10kΩ 33pF 10kΩ 33pF 10kΩ 33pF 10kΩ Figure 1. MAX2306 Typical Operating Circuit Voltage-Controlled Oscillator, Buffers, and Quadrature Generation The LO signal for downconversion is provided by a ...
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer Table 1. MAX2306 Control Register States OPERATIONAL ACTION MODE RESULT Shutdown pin completely SHUTDOWN powers down the chip 0 in shutdown register bit leaves SHUTDOWN serial port active 0 in ...
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CDMA IF VGAs and I/Q Demodulators Table 2. MAX2308 Control Register States OPERATIONAL ACTION MODE RESULT Shutdown pin completely shuts down SHUTDOWN chip 0 in shutdown register bit leaves seri- SHUTDOWN al port active 0 in standby pin turns off ...
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer 2.4kΩ 0.068µF 0.01µF 33pF 10kΩ 2pF 33pF 10kΩ Figure 2. MAX2308 Typical Operating Circuit 12 ______________________________________________________________________________________ 47pF 0.01µF 0.01µF BYP BYP 0.01µF MAX2308 CP_OUT BYP 0.01µF GND FM- ...
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CDMA IF VGAs and I/Q Demodulators Table 3. MAX2309 Control Register States OPERATIONAL ACTION MODE RESULT Shutdown pin com- SHUTDOWN pletely powers down the chip 0 in shutdown register SHUTDOWN bit leaves serial bus active 0 in standby pin turns ...
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer 0.068µF 2.4kΩ 10kΩ 10kΩ DISCRIMINATOR 455kHz V CC LIMITER I FM Figure 3. MAX2309 Typical Operating Circuit 14 ______________________________________________________________________________________ 47pF 0.01µF BYP BYP 0.01µF CP_OUT BYP GND STBY DIVSEL 33pF ...
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CDMA IF VGAs and I/Q Demodulators TANK_+ Figure 4. Voltage-Controlled Oscillators VCO_H DATA 13-BIT CONTROL VCO_L Figure 5. 3-Wire Control Block Diagram ______________________________________________________________________________________ with VCO and Synthesizer V CC 800µ ...
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MSB *SB DATA *START BIT MUST BE LOGIC HIGH. CLK RISE AND FALL REQUIRED PRIOR TO EN GOING LOW. EN Figure 6. 3-Wire Interface Timing Diagram Table 4. Control Register, ...
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CDMA IF VGAs and I/Q Demodulators START BIT SHIFT REGISTER 1 M1 REGISTER REGISTER CP1 AND R1 REGISTERS CP 1/1 CP2 AND R2 REGISTERS CP 2/1 /1 CTRL REGISTER TM Figure 7. Programming ...
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2306 MAX2308 MAX2309 SB 1 SHIFT REGISTER M1 REGISTER M2 REGISTER 2 CP1 R1 REGISTER 2 CP2 R2 REGISTER DS TM POL CONTROL 2 ...
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CDMA IF VGAs and I/Q Demodulators V CC FM- FM+ CDMA+ CDMA- BYP BYP MAX2306 TANKL+ BYP AGND TANKL- ______________________________________________________________________________________ with VCO and Synthesizer DAC AVCC QOUT+ QOUT- VGA DATA EN CLK PHASE CHARGE PUMP DETECTOR ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products 21 FM+ N ...