AD9661AKR Analog Devices Inc, AD9661AKR Datasheet - Page 7

• Manufacturer Part Number: AD9661AKR
• Description: IC LASER DIODE DRIVER 28-SOIC
• Manufacturer: Analog Devices Inc
• Type: Laser Diode Driverr

Specifications of AD9661AKR

• Rohs Status: RoHS non-compliant
• Number Of Channels: 1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Mounting Type: Surface Mount

REV. 0
Initial calibration is required after power-up or any other time
the laser has been disabled. Disabling the AD9661A drives the
hold capacitor to V
output current is more than 10% out of calibration, R will range
from 300
be used for calculating the worst case calibration time. Following
the example above, if C
calibration error < 1%, the initial calibration time should be
> 5 = 12.36 s.
Initial calibration time will actually be better than this calcula-
tion indicates, as a significant portion of the calibration time will
be within 10% of the final value, and the output resistance in
the AD9660’s T/H decreases as the hold voltage approaches its
final value.
Recalibration is functionally identical to initial calibration, but
the loop need only correct for droop. Because droop is assumed
to be a small percentage of the initial calibration (< 10%), the
resistance for the model above will be in the range of 75
140 . Again, the higher value should be used to estimate the
worst case time needed for recalibration.
Continuing with the example above, since the droop error dur-
ing hold time is < 5%, we meet the criteria for recalibration and
after recalibration, the 5% droop must be corrected to within a
20% error (20% 5% = 1%). A 2 recalibration time of 1.2 s
is sufficient.
Continuous Recalibration
In applications where the hold capacitor is small (< 500 pF) and
the WRITE PULSE signals always have a pulse width > 25 ns,
the user may continuously calibrate the feedback loop. In such
an application, the CAL signal should be held logic LOW, and
the PULSE signal will control loop calibration via the internal
AND gate. In such application, it is important to optimize the
layout for the TZA (POWER MONITOR, GAIN, R
C
= RC = 140
= RC = 550
GAIN
).
100
90
80
70
60
50
40
30
20
10
0
0
to 550
Figure 4. Calibration Time
4.5 nF = 0.64 s. To get a final error of 1%
4.5 nF would be 2.48 s. For an initial
1
for the model above; the higher value should
REF
. In this case, or in any case where the
HOLD
TIME CONSTANTS –
2
were chosen as 4.5 nF, then
3
4
GAIN
and
5
to
–7–
Driving the Analog Inputs
The POWER LEVEL input of the AD9661A drives the track
and hold amplifier and allows the user to adjust the amount of
output current as described above. The input voltage range is
V
V
on board level shift circuit). The circuit below will perform the
level shift and scale the output of a DAC whose output is from
ground to a positive voltage. This solution is especially attrac-
tive because both the DAC and the op amp can run off a single
+5 V supply, and the op amp doesn’t have to swing rail to rail.
Using the Level Shift Circuit
The AD9661A includes an on board level shift circuit to provide
the offset described above. The input, LEVEL SHIFT IN, has
an input range from 0.1 V to 1.6 V. The output, LEVEL
SHIFT OUT, has a range from V
drive POWER MONITOR. The linearity of the level shift cir-
cuit is poor for inputs below 100 mV. Between 100 mV and
1.6 V it is about 7 bits accurate.
Layout Considerations
As in all high speed applications, proper layout is critical; it is
particularly important when both analog and digital signals are
involved. Analog signal paths should be kept as short as
possible, and isolated from digital signals to avoid coupling in
noise. In particular, digital lines should be isolated from
OUTPUT, SENSE IN, POWER LEVEL, LEVEL SHIFT IN
POWER MONITOR, and HOLD traces. Digital signal paths
should also be kept short, and run lengths matched to avoid
propagation delay mismatch.
Layout of the ground and power supply circuits is also critical.
A single, low impedance ground plane will reduce noise on the
circuit ground. Power supplies should be capacitively coupled
to the ground plane to reduce noise in the circuit. 0.1 F
surface mount capacitors, placed as close as possible to the
AD9661A +V
diode meet this requirement. Multilayer circuit boards allow
designers to lay out signal traces without interrupting the ground
plane, and provide low impedance power planes to further
reduce noise.
REF
REF
DAC
to V
for a ground based signal (see below for description of the
REF
Figure 5. Driving the Analog Inputs
+ 1.6 V, requiring the user to create an offset of
V
S
DAC
connections, and the +V
R1
R2
V
REF
R1
+ V
DAC
OP191
REF
R2
R1
R2
+5V
= V
to V
POWER LEVEL
S
connection to the laser
REF
+1.6 V, and can
AD9661A
BIAS LEVEL
V
AD9661A
REF