PPC405GP-3BE266C Applied Micro Circuits Corporation, PPC405GP-3BE266C Datasheet - Page 33

• Manufacturer Part Number: PPC405GP-3BE266C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC405GP-3BE266C

• Family Name: 405GP
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 266MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 2.5V
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 456
• Package Type: EBGA
• Lead Free Status / Rohs Status: Not Compliant

Revision 2.05 – August 19, 2008
Signal Functional Description
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 29.
AMCC
PerCS1:7[GPIO10:16]
EOT0:3/TC0:3
Signal Name
DMAReq0:3
DMAAck0:3
PerReady
PerBLast
PerCS0
PerR/W
PerOE
Data Sheet
Peripheral chip select bank 0.
Seven additional peripheral chip selects
or
General Purpose I/O. To access this function, software must toggle a
DCR bit.
Used by either the peripheral controller or the DMA controller
depending upon the type of transfer involved. When the PPC405GP
is the bus master, it enables the selected device to drive the bus.
Used by the PPC405GP when not in external master mode, as output
by either the peripheral controller or DMA controller depending upon
the type of transfer involved. High indicates a read from memory, low
indicates a write to memory.
Otherwise it used by the external master as an input to indicate the
direction of data transfer.
Used by a peripheral slave to indicate it is ready to transfer data.
Used by the PPC405GP when not in external master mode,
otherwise used by external master. Indicates the last transfer of a
memory access.
DMAReq0:3 are used by slave peripherals to indicate they are
prepared to transfer data.
DMAAck0:3 are used by the PPC405GP to cause the DMA
peripheral to transfer data.
End Of Transfer/Terminal Count.
(Part 4 of 8)
Description
405GP – Power PC 405GP Embedded Processor
O[I/O]
I/O
I/O
I/O
I/O
O
O
O
I
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
Type
Notes
1, 7
1, 7
7
7
1
1
1
6
1
33