PPC405GP-3BE266C Applied Micro Circuits Corporation, PPC405GP-3BE266C Datasheet - Page 34

• Manufacturer Part Number: PPC405GP-3BE266C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC405GP-3BE266C

• Family Name: 405GP
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 266MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 2.5V
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 456
• Package Type: EBGA
• Lead Free Status / Rohs Status: Not Compliant

405GP – Power PC 405GP Embedded Processor
Signal Functional Description
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 29.
34
External Master Peripheral Interface
Internal Peripheral Interface
Signal Name
UART0_DCD
UART0_DSR
UART0_DTR
UARTSerClk
UART0_CTS
UART0_RTS
UART0_Rx
UART1_Rx
UART0_Tx
UART0_RI
ExtReset
HoldReq
HoldAck
BusReq
ExtReq
HoldPri
PerClk
ExtAck
PerErr
Peripheral clock to be used by an external master and by
synchronous peripheral slaves.
Peripheral reset to be used by an external master and by
synchronous peripheral slaves.
Hold Request, used by an external master to request ownership of
the peripheral bus.
Hold Acknowledge, used by the PPC405GP to transfer ownership of
peripheral bus to an external master.
ExtReq is used by an external master to indicate it is prepared to
transfer data.
ExtAck is used by the PPC405GP to indicate a data transfer cycle.
Used by an external master to indicate the priority of a given external
master tenure.
Used when the PPC405GP needs to regain control of peripheral
interface from an external master.
An input used to indicate to the PPC405GP that an external slave
peripheral error occurred.
Serial Clock used to provide an alternate clock to the internally
generated serial clock. Used in cases where the allowable internally
generated baud rates are not satisfactory. This input can be
individually connected to either UART.
UART0 Serial Data In.
UART0 Serial Data Out.
UART0 Data Carrier Detect.
UART0 Data Set Ready.
UART0 Clear To Send.
UART0 Data Terminal Ready.
UART0 Request To Send.
UART0 Ring Indicator.
UART1 Serial Data In.
(Part 5 of 8)
Description
Revision 2.05 – August 19, 2008
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AMCC