SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 24
SAM9263
Manufacturer Part Number
SAM9263
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9261.pdf
(248 pages)
5.SAM9263.pdf
(1109 pages)
6.SAM9263.pdf
(51 pages)
Specifications of SAM9263
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Can
1
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
NO
External Bus Interface
2
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9263 PDF datasheet #5
- SAM9263 PDF datasheet #6
- Current page: 24 of 284
- Download datasheet (2Mb)
Introduction
1.1
1.1.1
1-2
About the ARM7TDMI core
The instruction pipeline
The ARM7TDMI core is a member of the ARM family of general-purpose 32-bit
microprocessors. The ARM family offers high performance for very low power
consumption, and small size.
The ARM architecture is based on Reduced Instruction Set Computer (RISC)
principles. The RISC instruction set, and related decode mechanism are much simpler
than those of Complex Instruction Set Computer (CISC) designs. This simplicity gives:
•
•
•
This section describes:
•
•
•
•
The ARM7TDMI core uses a pipeline to increase the speed of the flow of instructions
to the processor. This allows several operations to take place simultaneously, and the
processing and memory systems to operate continuously.
A three-stage pipeline is used, so instructions are executed in three stages:
•
•
•
The instruction pipeline is shown in Figure 1-1 on page 1-3.
a high instruction throughput
an excellent real-time interrupt response
a small, cost-effective, processor macrocell.
The instruction pipeline on page 1-2
Memory access on page 1-3
Memory interface on page 1-4.
EmbeddedICE Logic on page 1-4.
Fetch
Decode
Execute.
Copyright © 1994-2001. All rights reserved.
ARM DDI 0029G
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