CY7C4261V-10JC Cypress Semiconductor Corp, CY7C4261V-10JC Datasheet - Page 4

• Manufacturer Part Number: CY7C4261V-10JC
• Description: IC DEEP SYNC FIFO 16KX9 32-PLCC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4261V-10JC

• Function: Synchronous
• Memory Size: 144K (16K x 9)
• Data Rate: 100MHz
• Access Time: 8ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1234

Document #: 38-06013 Rev. *A
It is not necessary to write to all the offset registers at one time.
A subset of the offset registers can be written; then by bringing
the WEN2/LD input HIGH, the FIFO is returned to normal read
and write operation. The next time WEN2/LD is brought LOW,
a write operation stores data in the next offset register in
sequence.
Note:
1.
8
8
8
8
8
8
8
8
Figure 1. Offset Register Location and Default Values
7
The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK.
7
7
7
7
7
Empty Offset (LSB) Reg.
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
Default Value = 000h
Empty Offset (LSB) Reg.
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
Default Value = 000h
16k x 9
64k x 9
5
5
Default Value = 000h
Default Value = 000h
(MSB)
(MSB)
(MSB)
(MSB)
0
0
0
0
0
0
0
0
8
8
8
8
8
8
8
8
7
7
7
7
Empty Offset (LSB) Reg.
Default Value = 007h
6
Full Offset (LSB) Reg
Default Value = 007h
Default Value = 000h
Default Value = 000h
Empty Offset (LSB) Reg.
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
6
32k x 9
128k x 9
Default Value = 000h
Default Value = 000h
(MSB)
(MSB)
(MSB)
(MSB)
0
0
0
0
0
0
0
0
The contents of the offset registers can be read to the data
outputs when WEN2/LD is LOW and both REN1 and REN2
are LOW. LOW-to-HIGH transitions of RCLK read register
contents to the data outputs. Writes and reads should not be
performed simultaneously on the offset registers.
Programmable Flag (PAE, PAF) Operation
Whether the flag offset registers are programmed as
described in Table 1 or the default values are used, the
programmable almost-empty flag (PAE) and programmable
almost-full flag (PAF) states are determined by their corre-
sponding offset registers and the difference between the read
and write pointers.
Table 1. Writing the Offset Registers
The number formed by the empty offset least significant bit
register and empty offset most significant bit register is
referred to as n and determines the operation of PAE. PAF is
synchronized to the LOW-to-HIGH transition of RCLK by one
flip-flop and is LOW when the FIFO contains n or fewer unread
words. PAE is set HIGH by the LOW-to-HIGH transition of
RCLK when the FIFO contains (n+1) or greater unread words.
The number formed by the full offset least significant bit
register and full offset most significant bit register is referred to
as m and determines the operation of PAF. PAE is synchronized to
the LOW-to-HIGH transition of WCLK by one flip-flop and is
set LOW when the number of unread words in the FIFO is
greater than or equal to CY7C4261V (16k – m), CY7C4271V
(32k – m), CY7C4281V (64k - m) and CY7C4291V (128k – m).
PAF is set HIGH by the LOW-to-HIGH transition of WCLK
when the number of available memory locations is greater
than m.
LD
0
0
1
1
WEN
0
1
0
1
WCLK
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
No Operation
Write Into FIFO
No Operation
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
[1]
Selection
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