CY7C4261-15JXC Cypress Semiconductor Corp, CY7C4261-15JXC Datasheet - Page 5

• Manufacturer Part Number: CY7C4261-15JXC
• Description: IC DEEP SYNC FIFO 16KX9 32-PLCC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4261-15JXC

• Function: Synchronous
• Memory Size: 144K (16K x 9)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-PLCC
• Configuration: Dual
• Density: 144Kb
• Access Time (max): 10ns
• Word Size: 9b
• Organization: 16Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 35mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

It is not necessary to write to all the offset registers at one time.
A subset of the offset registers can be written, and then by
bringing the WEN2/LD input HIGH, the FIFO is returned to
normal read and write operation. The next time WEN2/LD is
brought LOW, a write operation stores data in the next offset
register in sequence.
The contents of the offset registers can be read to the data
outputs when WEN2/LD is LOW and both REN1 and REN2 are
LOW. LOW-to-HIGH transitions of RCLK read register contents
to the data outputs. Writes and reads must not be performed
simultaneously on the offset registers.
Programmable Flag (PAE, PAF) Operation
Whether the flag offset registers are programmed as described
in
almost-empty flag (PAE) (PAF) states are determined by their
corresponding offset registers and the difference between the
read and write pointers.
Table 2. Writing the Offset Registers
The number formed by the empty offset least significant bit
register and empty offset most significant bit register is referred
to as n and determines the operation of PAE. PAF is synchronized
to the LOW-to-HIGH transition of RCLK by one flip-flop and is
LOW when the FIFO contains n or fewer unread words. PAE is
set HIGH by the LOW-to-HIGH transition of RCLK when the
FIFO contains (n+1) or greater unread words.
The number formed by the full offset least significant bit register
and full offset most significant bit register is referred to as m and
determines the operation of PAF. PAE is synchronized to the
LOW-to-HIGH transition of WCLK by one flip-flop and is set LOW
when the number of unread words in the FIFO is greater than or
equal to CY7C4261 (16K-m) and CY7C4271 (32K-m). PAF is set
HIGH by the LOW-to-HIGH transition of WCLK when the number
of available memory locations is greater than m.
Notes
Document #: 38-06015 Rev. *D
1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK.
2. n = Empty Offset (n = 7 default value).
3. m = Full Offset (m = 7 default value).
LD
Table 2
0
0
1
1
WEN
0
1
0
1
or the default values are used, the programmable
WCLK
[1]
No Operation
Write Into FIFO
No Operation
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Selection
Table 3. Status Flags
Width Expansion Configuration
Word width may be increased by simply connecting the
corresponding input controls signals of multiple devices. A
composite flag must be created for each of the end-point status
flags (EF and FF). The partial status flags (PAE and PAF) can be
detected from any one device.
a 18-bit word width by using two CY7C4261/71s. Any word width
can be attained by adding additional CY7C4261/71s.
When the CY7C4261/71 is in a Width Expansion Configuration,
the Read Enable (REN2) control input can be grounded (see
Figure 4
2/Load (WEN2/LD) pin is set to LOW at Reset so that the pin
operates as a control to load and read the programmable flag
offsets.
Flag Operation
The CY7C4261/71 devices provide four flag pins to indicate the
condition of the FIFO contents. Empty, Full, PAE, and PAF are
synchronous.
Full Flag
The Full Flag (FF) goes LOW when the device is full. Write
operations are inhibited whenever FF is LOW regardless of the
state of WEN1 and WEN2/LD. FF is synchronized to WCLK, that
is, it is exclusively updated by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF) goes LOW when the device is empty. Read
operations are inhibited whenever EF is LOW, regardless of the
state of REN1 and REN2. EF is synchronized to RCLK, that is, it
is exclusively updated by each rising edge of RCLK.
0
1 to n
(n + 1) to
(16384 − (m + 1))
(16384 − m)
16384
CY7C4261
[2]
Number of Words in FIFO
on page 6). In this configuration, the Write Enable
[3]
to 16383 (32768 − m)
0
1 to n
(n + 1) to
(32768 − (m + 1))
32768
CY7C4261, CY7C4261
CY7C4271
[2]
Figure 4
[3]
to 32767 H
on page 6 demonstrates
FF PAF PAE EF
H
H
H
L
H
H
H
L
L
Page 5 of 19
H
H
H
L
L
H
H
H
H
L
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