EPF10K10 ETC, EPF10K10 Datasheet - Page 3

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EPF10K10

Manufacturer Part Number
EPF10K10
Description
EMBEDDED PROGRAMMABLE LOGIC FAMILY
Manufacturer
ETC
Datasheet

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Altera Corporation
Flexible interconnect
Powerful I/O pins
Peripheral register for fast setup and clock-to-output delay
Flexible package options
Software design support and automatic place-and-route provided by
Altera’s MAX+PLUS
PCs and Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC
System/6000 workstations, and Quartus
Windows-based PCs and Sun SPARCstation and HP 9000 Series 700
workstations
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
DesignWare components, Verilog HDL, VHDL, and other interfaces
to popular EDA tools from manufacturers such as Cadence,
Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity,
VeriBest, and Viewlogic
FastTrack
predictable interconnect delays
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
Tri-state emulation that implements internal tri-state buses
Up to six global clock signals and four global clear signals
Individual tri-state output enable control for each pin
Open-drain option on each I/O pin
Programmable output slew-rate control to reduce switching
noise
FLEX 10KA devices support hot-socketing
Available in a variety of packages with 84 to 600 pins (see
Table
Pin-compatibility with other FLEX 10K devices in the same
package
FineLine BGA
FLEX 10K Embedded Programmable Logic Family Data Sheet
4)
®
Interconnect continuous routing structure for fast,
TM
®
packages maximize board space efficiency
II development system for Windows-based
TM
development system for
3

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