EPF10K10 ETC, EPF10K10 Datasheet - Page 56

• Manufacturer Part Number: EPF10K10
• Description: EMBEDDED PROGRAMMABLE LOGIC FAMILY
• Manufacturer: ETC

56
FLEX 10K Embedded Programmable Logic Family Data Sheet
t
t
t
t
t
t
t
t
t
t
LUT
CLUT
RLUT
PACKED
EN
CICO
CGEN
CGENR
CASC
C
Table 32. LE Timing Microparameters (Part 1 of 2)
Symbol
LUT delay for data-in
LUT delay for carry-in
LUT delay for LE register feedback
Data-in to packed register delay
LE register enable delay
Carry-in to carry-out delay
Data-in to carry-out delay
LE register feedback to carry-out delay
Cascade-in to cascade-out delay
LE register control signal delay
Figure 28. Synchronous Bidirectional Pin External Timing Model
Note:
(1)
Tables 32
parameters. These internal timing parameters are expressed as worst-case
values. Using hand calculations, these parameters can be used to estimate
design performance. However, before committing designs to silicon,
actual worst-case performance should be modeled using timing
simulation and analysis.
timing parameters.
The output enable and input registers are LE registers in the lab adjacent to the
bidirectional pin.
Dedicated
Clock
through
Parameter
36
describe the FLEX 10K device internal timing
Tables 37
Note (1)
IOE Register
D
D
D
CLRN
CLRN
CLRN
PRN
PRN
PRN
through
(1)
(1)
Q
Q
Q
39
describe FLEX 10K external
Altera Corporation
Bidirectional
Pin
Conditions