ADA4000-1ARZ Analog Devices Inc, ADA4000-1ARZ Datasheet - Page 10

• Manufacturer Part Number: ADA4000-1ARZ
• Description: IC OPAMP JFET 5MHZ PREC LP 8SOIC
• Manufacturer: Analog Devices Inc

Specifications of ADA4000-1ARZ

• Slew Rate: 20 V/µs
• Design Resources: Power off protected data acquisition signal chain using ADG4612 , AD711, and AD7476 (CN0165)
• Amplifier Type: J-FET
• Number Of Circuits: 1
• Gain Bandwidth Product: 5MHz
• Current - Input Bias: 5pA
• Voltage - Input Offset: 200µV
• Current - Supply: 1.35mA
• Current - Output / Channel: 28mA
• Voltage - Supply, Single/dual (±): 8 V ~ 36 V, ±4 V ~ 18 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Op Amp Type: Low Power
• No. Of Amplifiers: 1
• Bandwidth: 5MHz
• Supply Voltage Range: ± 4V To ± 18V
• Amplifier Case Style: SOIC
• No. Of Pins: 8
• Operating Temperature Range: -40°C To
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• -3db Bandwidth: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADA4000-1/ADA4000-2/ADA4000-4
APPLICATIONS
OUTPUT PHASE REVERSAL AND INPUT NOISE
Phase reversal is a change of polarity in the transfer function of
the amplifier. This can occur when the voltage applied at the
input of the amplifier exceeds the maximum common-mode
voltage. Phase reversal happens when the part is configured in
the gain of 1.
Most JFET amplifiers invert the phase of the input signal if the
input exceeds the common-mode input. Phase reversal is a
temporary behavior of the ADA4000-x family. Each part
returns to normal operation by bringing back the common-
mode voltage. The cause of this effect is saturation of the input
stage, which leads to the forward-biasing of a drain-gate diode.
In noninverting applications, a simple fix for this is to insert a
series resistor between the input signal and the noninverting
terminal of the amplifier. The value of the resistor depends on
the application, because adding a resistor adds to the total input
noise of the amplifier. The total noise density of the circuit is
where:
e
i
R
k is Boltzmann’s constant (1.38 × 10
T is the ambient temperature in Kelvin (T = 273 + °C).
In general, it is good practice to limit the input current to less
than 5 mA to avoid driving a great deal of current into the
amplifier inputs.
CAPACITIVE LOAD DRIVE
The ADA4000-1/ADA4000-2/ADA4000-4 are stable at all gains
in both inverting and noninverting configurations. The parts
are capable of driving up to 1000 pF of capacitive loads without
oscillations in unity gain configurations.
However, as with most amplifiers, driving larger capacitive loads
in a unity gain configuration can cause excessive overshoot and
ringing. A simple solution to this problem is to use a snubber
network (see Figure 30).
n
n
S
is the input current noise density of the part.
is the input voltage noise density of the part.
400mV p-p
is the source resistance at the noninverting terminal.
e
nTOTAL
=
0
Figure 30. Snubber Network Configuration
V1
e
n
3
2
2
+
ADA4000-1
(
i
n
+15V
–15V
R
V+
V–
S
)
2
U1
+
4
kTR
1
SNUBBER NETWORK
−23
S
J/K).
C
R
S
S
0
C
500pF
L
R
10kΩ
L
Rev. A | Page 10 of 16
The advantage of this compensation method is that the swing at
the output is not reduced because R
network, and the gain accuracy does not change. Depending on
the capacitive loading of the circuit, the values of R
change, and the optimum value can be determined empirically.
In Figure 31, the oscilloscope image shows the output of the
ADA4000-x family in response to a 400 mV pulse. The circuit is
configured in the unity gain configuration with 500 pF in
parallel with 10 kΩ of load capacitive.
When the snubber circuit is used, the overshoot is reduced from
30% to 6% with the same load capacitance. Ringing is virtually
eliminated, as shown in Figure 32. In this circuit, R
C
S
is 10 nF.
Figure 31. Capacitive Load Drive Without Snubber Network
Figure 32. Capacitive Load with Snubber Network
OUTPUT SIGNAL
INPUT SIGNAL
OUTPUT SIGNAL
INPUT SIGNAL
TIME (1µs/DIV)
TIME (1µs/DIV)
S
is out of the feedback
S
S
and C
is 41 Ω and
S