DSP56321VF220 Freescale Semiconductor, DSP56321VF220 Datasheet - Page 19

• Manufacturer Part Number: DSP56321VF220
• Description: IC DSP 24BIT 220MHZ 196-BGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of DSP56321VF220

• Interface: Host Interface, SSI, SCI
• Clock Rate: 220MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 576kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.60V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: *
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 220MHz
• Mips: 220
• Device Input Clock Speed: 220MHz
• Ram Size: 576KB
• Operating Supply Voltage (typ): 1.6/3.3V
• Operating Supply Voltage (min): 1.5/3/3/3/3/3/3V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Package: 196MA-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 220 MHz
• Device Million Instructions Per Second: 220 MIPS
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

1.10 Timers
The DSP56321 has three identical and independent timers. Each timer can use internal or external clocking and can
either interrupt the DSP56321 after a specified number of events (clocks) or signal an external device after
counting a specific number of internal events.
Freescale Semiconductor
SCLK
PE2
Notes:
TIO0
TIO1
TIO2
Notes:
Signal Name
Signal Name
1.
2.
1.
2.
In the Stop state, the signal maintains the last state as follows:
• If the last state is input, the signal is an ignored input.
• If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated.
The Wait processing state does not affect the signal state.
In the Stop state, the signal maintains the last state as follows:
• If the last state is input, the signal is an ignored input.
• If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated.
The Wait processing state does not affect the signal state.
Input/Output
Input or Output
Input or Output
Input or Output
Input or Output
Type
Type
Table 1-13.
Ignored Input
Ignored Input
Ignored Input
State During
State During
Ignored Input
Reset
Reset
Table 1-14.
DSP56321 Technical Data, Rev. 11
Serial Communication Interface (Continued)
1,2
1,2
Serial Clock—Provides the input or output clock used by the transmitter and/or
the receiver.
Port E 2—The default configuration following reset is GPIO input PE2. When
configured as PE2, signal direction is controlled through the Port E Direction
Register. The signal can be configured as an SCI signal SCLK through the Port
E Control Register.
Timer 0 Schmitt-Trigger Input/Output— When Timer 0 functions as an
external event counter or in measurement mode, TIO0 is used as input. When
Timer 0 functions in watchdog, timer, or pulse modulation mode, TIO0 is used
as output.
The default mode after reset is GPIO input. TIO0 can be changed to output or
configured as a timer I/O through the Timer 0 Control/Status Register (TCSR0).
Timer 1 Schmitt-Trigger Input/Output— When Timer 1 functions as an
external event counter or in measurement mode, TIO1 is used as input. When
Timer 1 functions in watchdog, timer, or pulse modulation mode, TIO1 is used
as output.
The default mode after reset is GPIO input. TIO1 can be changed to output or
configured as a timer I/O through the Timer 1 Control/Status Register (TCSR1).
Timer 2 Schmitt-Trigger Input/Output— When Timer 2 functions as an
external event counter or in measurement mode, TIO2 is used as input. When
Timer 2 functions in watchdog, timer, or pulse modulation mode, TIO2 is used
as output.
The default mode after reset is GPIO input. TIO2 can be changed to output or
configured as a timer I/O through the Timer 2 Control/Status Register (TCSR2).
Triple Timer Signals
Signal Description
Signal Description
Timers
1-13