CY7C4261-10JXI Cypress Semiconductor Corp, CY7C4261-10JXI Datasheet - Page 11

• Manufacturer Part Number: CY7C4261-10JXI
• Description: IC,FIFO,16KX9,SYNCHRONOUS,CMOS,LDCC,32PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4261-10JXI

• Function: Synchronous
• Memory Size: 144K (16K x 9)
• Data Rate: 100MHz
• Access Time: 8ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-PLCC
• Configuration: Dual
• Density: 144Kb
• Access Time (max): 8ns
• Word Size: 9b
• Organization: 16Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 40mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Waveforms
Notes
Document Number: 38-06015 Rev. *G
16. The clocks (RCLK, WCLK) can be free running during reset.
17. After reset, the outputs are LOW if OE = 0 and three-state if OE = 1.
18. Holding WEN2/LD HIGH during reset makes the pin act as a second enable pin. Holding WEN2/LD LOW during reset makes the pin act as a load enable for the
19. When t
20. The first word is available the cycle after EF goes HIGH, always.
programmable flag offset registers.
t
SKEW1
WEN2/LD
. The Latency Timing applies only at the Empty Boundary (EF = LOW).
(if applicable)
SKEW1
Q
EF,PAE
FF,PAF
Q
D
WEN2
WEN1
REN1,
WEN1
WCLK
REN1,
0 -
REN2
RCLK
0
0
REN2
–D
–Q
RS
> minimum specification, t
OE
[18]
EF
Q
8
8
8
t
ENS
t
DS
Figure 9. First Data Word Latency after Reset with Read and Write
D
(continued)
0
(FIRST VALID WRITE)
FRL
(maximum) = t
t
SKEW1
t
t
t
RSF
RSF
RSF
t
RS
t
CLK
OLZ
t
FRL
Figure 8. Reset Timing
+ t
t
t
t
RSS
RSS
RSS
[19]
SKEW2
t
. When t
D
REF
1
SKEW2
t
OE
< minimum specification, t
[16]
t
D
A
2
[20]
t
t
t
RSR
RSR
RSR
FRL
CY7C4261, CY7C4271
(maximum) = either 2 × t
D
0
t
A
D
3
OE = 0
OE = 1
CLK
D
+ t
[17]
1
Page 11 of 21
D
SKEW1
4
or t
CLK
+
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