CY7C4261-10JXI Cypress Semiconductor Corp, CY7C4261-10JXI Datasheet - Page 20

• Manufacturer Part Number: CY7C4261-10JXI
• Description: IC,FIFO,16KX9,SYNCHRONOUS,CMOS,LDCC,32PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4261-10JXI

• Function: Synchronous
• Memory Size: 144K (16K x 9)
• Data Rate: 100MHz
• Access Time: 8ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-PLCC
• Configuration: Dual
• Density: 144Kb
• Access Time (max): 8ns
• Word Size: 9b
• Organization: 16Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 40mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document History Page
Document Number: 38-06015 Rev. *G
Document Title: CY7C4261/CY7C4271 16K/32 K × 9 Deep Sync FIFOs
Document Number: 38-06015
REV.
*A
*B
*C
*D
*E
*G
*F
**
2556036
2896039
3055213
3056210
106476
122267
127853
393437
ECN
VKN/AESA
Orig. of
Change
RAME
ADMU
ADMU
FSG
ESH
SZV
RBI
Submission
08/22/2008 Updated ordering information and data sheet template. Removed Pb-Free
03/19/2010 Updated package diagrams
10/13/2010 Removed CY7C4271-15AC from
11/02/2010
See ECN
09/10/01
12/26/02
08/22/03
Date
Changed from Spec number: 38-00658 to 38-06015
Added power up requirements Maximum Ratings Information
Switching Waveforms section: fixed misplaced footnote in t
Word Latency after Reset with Read and Write” drawing
Switching Waveforms section: changed t
Timing” drawing
Added Pb-Free Logo to top of front page
Added CY7C4261-10JXI, CY7C4261-15JXC to ordering information
Logo.
Removed inactive parts from Ordering information table
Updated links in Sales, Solutions and Legal Information
Code
■
■
■
■
■
■
Updated
Corrected data(typo) in
❐
❐
Updated
and 35.
Updated
and 35.
Updated
Updated
Updated “PAF is synchronized to the LOW-to-HIGH transition of RCLK by
one flip-flop and is LOW when the FIFO contains n or fewer unread words.”
to read as “PAE is synchronized to the LOW-to-HIGH transition of RCLK
by one flip-flop and is LOW when the FIFO contains n or fewer unread
words.”
Updated “PAE is synchronized to the LOW-to-HIGH transition of WCLK by
one flip-flop and is set LOW when the number of unread words in the FIFO
is greater than or equal to CY7C4261 (16K-m) and CY7C4271 (32K-m).”
to read as “PAF is synchronized to the LOW-to-HIGH transition of WCLK
by one flip-flop and is set LOW when the number of unread words in the
FIFO is greater than or equal to CY7C4261 (16K-m) and CY7C4271
(32K-m).”
Definitions.
Electrical
Switching
Selection
Ordering
Package
Information.
Diagrams.
Characteristics. Removed information for speed pins 25
Guide. Removed information for speed pins 25 and 35.
Characteristics. Removed information for speed pins 25
Programmable Flag (PAE, PAF)
Description of Change
Ordering Information
SKEW2
CY7C4261, CY7C4271
to t
SKEW1
and added
(typo) in “Empty Flag
Operation.
A
in “First Data
Page 20 of 21
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