CY7C4261-10JXI Cypress Semiconductor Corp, CY7C4261-10JXI Datasheet - Page 13

• Manufacturer Part Number: CY7C4261-10JXI
• Description: IC,FIFO,16KX9,SYNCHRONOUS,CMOS,LDCC,32PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4261-10JXI

• Function: Synchronous
• Memory Size: 144K (16K x 9)
• Data Rate: 100MHz
• Access Time: 8ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-PLCC
• Configuration: Dual
• Density: 144Kb
• Access Time (max): 8ns
• Word Size: 9b
• Organization: 16Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 40mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Waveforms
Notes
Document Number: 38-06015 Rev. *G
23. t
24. PAE offset = n.
25. If a read is preformed on this rising edge of the read clock, there are Empty + (n1) words in the FIFO when PAE goes LOW
26. If a write is performed on this rising edge of the write clock, there are Full  (m1) words of the FIFO when PAF goes LOW.
27. PAF offset = m.
28. 16,384  m words for CY7C4261, 32,768  m words for CY7C4271.
29. t
and the rising RCLK is less than t
RCLK and the rising edge of WCLK is less than t
(if applicable)
SKEW2
SKEW2
(if applicable)
WEN2
WCLK
REN1,
WEN1
RCLK
REN2
is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK
is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of
WEN2
PAE
WCLK
WEN1
REN1,
RCLK
REN2
PAF
t
CLKH
t
CLKH
SKEW2
(continued)
FULL  (M + 1) WORDS
, then PAE may not change state until the next RCLK.
t
ESKEW2
Figure 12. Programmable Almost Empty Flag Timing
Figure 13. Programmable Almost Full Flag Timing
IN FIFO
SKEW2
t
t
ENS
ENS
[23]
t
t
ENS
ENS
, then PAF may not change state until the next WCLK.
t
t
ENH
ENH
t
t
ENH
ENH
t
CLKL
t
CLKL
t
PAE
24
Note
26
27
t
PAF
t
ENS
t
ENS
t
SKEW2
FULL  M WORDS
N + 1 WORDS
IN FIFO
t
ENS
IN FIFO
[29]
t
ENS
[28]
t
ENH
CY7C4261, CY7C4271
t
ENH
t
PAF
25
Page 13 of 21
t
PAE
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