EP20K200EFC484-3 Altera, EP20K200EFC484-3 Datasheet - Page 31

• Manufacturer Part Number: EP20K200EFC484-3
• Description: IC APEX 20KE FPGA 200K 484-FBGA
• Manufacturer: Altera
• Series: APEX-20K®r

Specifications of EP20K200EFC484-3

• Number Of Logic Elements/cells: 8320
• Number Of Labs/clbs: 832
• Total Ram Bits: 81920
• Number Of I /o: 376
• Number Of Gates: 404000
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: APEX 20K
• Number Of Usable Gates: 200000
• Number Of Logic Blocks/elements: 8320
• # Registers: 52
• # I/os (max): 376
• Frequency (max): 189MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.8V
• Logic Cells: 8320
• Ram Bits: 106496
• Device System Gates: 526000
• Operating Supply Voltage (min): 1.71V
• Operating Supply Voltage (max): 1.89V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-1099

Altera Corporation
Figure 18. Deep Memory Block Implemented with Multiple ESBs
The ESB implements two forms of dual-port memory: read/write clock
mode and input/output clock mode. The ESB can also be used for
bidirectional, dual-port memory applications in which two ports read or
write simultaneously. To implement this type of dual-port memory, two
or four ESBs are used to support two simultaneous reads or writes. This
functionality is shown in
Figure 19. APEX 20K ESB Implementing Dual-Port RAM
Clock A
APEX 20K Programmable Logic Device Family Data Sheet
ESB
ESB
ESB
Address Decoder
address_a[]
data_a[]
we_a
clkena_a
Figure
Port A
19.
address_b[]
clkena_b
Port B
data_b[]
we_b
to System Logic
Clock B
31