EP20K200EFC484-3 Altera, EP20K200EFC484-3 Datasheet - Page 33

• Manufacturer Part Number: EP20K200EFC484-3
• Description: IC APEX 20KE FPGA 200K 484-FBGA
• Manufacturer: Altera
• Series: APEX-20K®r

Specifications of EP20K200EFC484-3

• Number Of Logic Elements/cells: 8320
• Number Of Labs/clbs: 832
• Total Ram Bits: 81920
• Number Of I /o: 376
• Number Of Gates: 404000
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: APEX 20K
• Number Of Usable Gates: 200000
• Number Of Logic Blocks/elements: 8320
• # Registers: 52
• # I/os (max): 376
• Frequency (max): 189MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.8V
• Logic Cells: 8320
• Ram Bits: 106496
• Device System Gates: 526000
• Operating Supply Voltage (min): 1.71V
• Operating Supply Voltage (max): 1.89V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-1099

Altera Corporation
Figure 21. ESB in Input/Output Clock Mode
Notes to
(1)
(2)
All registers can be cleared asynchronously by ESB local interconnect signals, global signals, or the chip-wide reset.
APEX 20KE devices have four dedicated clocks.
Figure
wraddress[ ]
rdaddress[ ]
outclock
outclken
inclken
inclock
data[ ]
Dedicated Clocks
21:
wren
rden
(2)
2 or 4
Dedicated Inputs &
Global Signals
Input/Output Clock Mode
The input/output clock mode contains two clocks. One clock controls all
registers for inputs into the ESB: data input, WE, RE, read address, and
write address. The other clock controls the ESB data output registers. The
ESB also supports clock enable and asynchronous clear signals; these
signals also control the reading and writing of registers independently.
Input/output clock mode is commonly used for applications where the
reads and writes occur at the same system frequency, but require different
clock enable signals for the input and output registers.
the ESB in input/output clock mode.
Single-Port Mode
The APEX 20K ESB also supports a single-port mode, which is used when
simultaneous reads and writes are not required. See
4
Note (1)
D
ENA
D
ENA
D
ENA
APEX 20K Programmable Logic Device Family Data Sheet
Q
Q
Q
D
ENA
D
ENA
Generator
Pulse
Write
Q
Q
Data In
Read Address
Write Address
Read Enable
Write Enable
RAM/ROM
1,024 × 2
2,048 × 1
Data Out
128 × 16
256 × 8
512 × 4
Figure
D
ENA
Figure 21
Q
22.
shows
to MegaLAB,
FastTrack &
Local
Interconnect
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