EP20K200EFC484-3 Altera, EP20K200EFC484-3 Datasheet - Page 41

IC APEX 20KE FPGA 200K 484-FBGA

EP20K200EFC484-3

Manufacturer Part Number
EP20K200EFC484-3
Description
IC APEX 20KE FPGA 200K 484-FBGA
Manufacturer
Altera
Series
APEX-20K®r
Datasheet

Specifications of EP20K200EFC484-3

Number Of Logic Elements/cells
8320
Number Of Labs/clbs
832
Total Ram Bits
81920
Number Of I /o
376
Number Of Gates
404000
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
APEX 20K
Number Of Usable Gates
200000
Number Of Logic Blocks/elements
8320
# Registers
52
# I/os (max)
376
Frequency (max)
189MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.8V
Logic Cells
8320
Ram Bits
106496
Device System Gates
526000
Operating Supply Voltage (min)
1.71V
Operating Supply Voltage (max)
1.89V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1099

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Figure 26. APEX 20KE Bidirectional I/O Registers
Notes to
(1)
(2)
Altera Corporation
Row, Column, FastRow,
or Local Interconnect
This programmable delay has four settings: off and three levels of delay.
The output enable and input registers are LE registers in the LAB adjacent to the bidirectional pin.
Figure
26:
4 Dedicated
Inputs
Clock Inputs
4 Dedicated
4
Peripheral Control
Bus
12
VCC
OE[7..0]
CLK[1..0]
CLK[3..0]
ENA[5..0]
CLRn[1..0]
VCC
Input Pin to Input
Core to Output
Register Delay
Register Delay
VCC
VCC
VCC
VCC
VCC
APEX 20K Programmable Logic Device Family Data Sheet
Chip-Wide
Chip-Wide
Chip-Wide Reset
Core Delay (1)
Core Delay (1)
Input Pin to
Clock Enable
Input Pin to
Reset
Reset
Delay (1 )
Notes
Output Enable
Output Register
Chip-Wide
Input Register
OE Register
ENA
D
D
ENA
D
ENA
(1),
CLRN
CLRN
CLRN/
PRN
Q
Q
Q
(2)
Open-Drain
Slew-Rate
Output
Control
Core Delay (1)
Output Register
Input Pin to
t
CO
Delay
VCCIO
Optional
PCI Clamp
41

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