LRS1331C Sharp Electronics, LRS1331C Datasheet - Page 18

• Manufacturer Part Number: LRS1331C
• Manufacturer: Sharp Electronics

Specifications of LRS1331C

• Lead Free Status / Rohs Status: Not Compliant

12.4 Write Cycle (F-CE Controlled)
Notes:
1. In systems where F-CE defines the write pulse width (within a longer F-WE timing waveform), all setup, hold and inactive
2. Sampled, not 100% tested.
3. Refer to Section 5. Command Definitions for Flash Memory for valid A
4. F-V
5. It is written when F-CE and F-WE are active. The address and data needed to execute a command are latched on the rising
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
EHWH
WLEL
DVEH
EHDX
EHAX
QVVL
AVEH
EHGL
AVAV
PHEL
ELEH
SHEH
VPEH
EHEL
EHRL
QVSL
F-WE times should be measured relative to the F-CE waveform.
write or lock-bit configuration.
success (SR.1/3/4/5=0).
edge of F-WE or F-CE (Whichever goes high first).
CCW
Write Cycle Time
F-RP High Recovery to F-CE Going Low
F-WE Setup to F-CE Going Low
F-CE Pulse Width
F-WP V
F-V
Address Setup to F-CE Going High
Data Setup to F-CE Going High
Data Hold from F-CE High
Address Hold from F-CE High
F-WE Hold from F-CE High
F-CE Pulse Width High
F-CE going High to F-RY/BY Going Low or SR.7 Going “0”
Write Recovery before Read
F-V
F-WP V
should be held at V
CCW
CC
Hold from Valid SRD, F-RY/BY High-Z
IH
IH
Setup to F-CE Going High
Setup to F-CE Going High
Hold from Valid SRD, F-RY/BY High-Z
CCWH
(1,5)
until determination of block erase, full chip erase, word write or lock-bit configuration
Parameter
L R S 1 3 3 1 C
IN
and D
(T
Notes
A
2,4
2,4
2
2
2
3
3
IN
= -25°C to +85°C, V
for block erase, full chip erase, word
Min.
100
100
90
65
50
50
25
1
0
0
0
0
0
0
0
Max.
100
CC
= 2.7V to 3.3V)
Unit
Rev. 1.00
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
16