LRS1331C Sharp Electronics, LRS1331C Datasheet - Page 31

• Manufacturer Part Number: LRS1331C
• Manufacturer: Sharp Electronics

Specifications of LRS1331C

• Lead Free Status / Rohs Status: Not Compliant

15. Notes
This product is a stacked CSP package that a 16M (x16) bit Flash Memory and a 4M (x16) bit SRAM are assembled into.
- Supply Power
- Power Supply and Chip Enable of Flash Memory and SRAM
- Power Up Sequence
- Device Decoupling
Maximum difference (between F-V
S-CE
If the two memories are active together, possibly they may not operate normally by interference noises or data collision
on DQ bus.
Both F-V
data retention mode.
When turning on Flash memory power supply, keep F-RP “low”. After F-V
more than 100nsec.
The power supply is needed to be designed carefully because one of the SRAM and the Flash Memory is in standby
mode when the other is active. A careful decoupling of power supplies is necessary between SRAM and Flash
Memory. Note peak current caused by transition of control signals (F-CE, S-CE
1
should not be “low” and S-CE
CC
and S-V
CC
are needed to be applied by the recommended supply voltage at the same time expect SRAM
CC
2
and S-V
should not be “high” when F-CE is “low” simultaneously.
L R S 1 3 3 1 C
CC
) of the voltage is less than 0.3V.
CC
reaches over 2.7V, keep F-RP “low” for
1
, S-CE
2
).
Rev. 1.00
29