LRS1331C Sharp Electronics, LRS1331C Datasheet - Page 23

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LRS1331C

Manufacturer Part Number
LRS1331C
Description
Manufacturer
Sharp Electronics
Datasheet

Specifications of LRS1331C

Lead Free Status / Rohs Status
Not Compliant
12.7 Reset Operations
Notes:
1. If F-RP is asserted while a block erase, full chip erase, word write or lock-bit configuration operation is not executing, the
2. A reset time, t
3. When the device power-up, holding F-RP low minimum 100ns is required after F-V
AC Waveform for Reset Operation
Symbol
t
t
t
PLPH
PLRZ
reset will complete within 100ns.
valid. Refer to AC Characteristics-Read Cycle for t
has been in stable there.
VPH
F-RP Pulse Low Time
(If F-RP is tied to V
F-RP Low to Reset during Block Erase, Full Chip Erase, Word
Write or lock-bit configuration
F-V
CC
PHQV
= 2.7V to F-RP High
(1,2)
, is required from the later of F-RY/BY(SR.7) going High-Z (“1”), or F-RP going high until outputs are
CC
, this specification is not applicable.)
Parameter
PHQV
L R S 1 3 3 1 C
.
Notes
3
(T
A
CC
= -25°C to +85°C, V
has been in predefined range and also
Min.
100
100
Max.
CC
30
= 2.7V to 3.3V)
Rev. 1.00
Unit
ns
µs
ns
21

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