PIC18LF452 Microchip Technology, PIC18LF452 Datasheet - Page 21

• Manufacturer Part Number: PIC18LF452
• Description: (PIC18LFxx2) Enhanced FLASH Microcontrollers
• Manufacturer: Microchip Technology

2.4
The EC and ECIO Oscillator modes require an external
clock source to be connected to the OSC1 pin. The
feedback device between OSC1 and OSC2 is turned
off in these modes to save current. There is no oscilla-
tor start-up time required after a Power-on Reset or
after a recovery from SLEEP mode.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-4 shows the pin connections for the EC
Oscillator mode.
FIGURE 2-4:
The ECIO Oscillator mode functions like the EC mode,
except that the OSC2 pin becomes an additional gen-
eral purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 2-5 shows the pin connections
for the ECIO Oscillator mode.
FIGURE 2-6:
2002 Microchip Technology Inc.
Clock from
Ext. System
(from Configuration
bit Register)
External Clock Input
OSC1
OSC2
F
OSC
/4
EXTERNAL CLOCK INPUT
OPERATION
(EC CONFIGURATION)
PLL BLOCK DIAGRAM
Crystal
PLL Enable
Osc
HS Osc
OSC1
OSC2
F
PIC18FXXX
IN
Comparator
F
OUT
Phase
Loop
Filter
FIGURE 2-5:
2.5
A Phase Locked Loop circuit is provided as a program-
mable option for users that want to multiply the fre-
quency of the incoming crystal oscillator signal by 4.
For an input clock frequency of 10 MHz, the internal
clock frequency will be multiplied to 40 MHz. This is
useful for customers who are concerned with EMI due
to high frequency crystals.
The PLL can only be enabled when the oscillator con-
figuration bits are programmed for HS mode. If they are
programmed for any other mode, the PLL is not
enabled and the system clock will come directly from
OSC1.
The PLL is one of the modes of the FOSC<2:0> config-
uration bits. The Oscillator mode is specified during
device programming.
A PLL lock timer is used to ensure that the PLL has
locked before device execution starts. The PLL lock
timer has a time-out that is called T
Divide by 4
Clock from
Ext. System
HS/PLL
RA6
VCO
EXTERNAL CLOCK INPUT
OPERATION
(ECIO CONFIGURATION)
PIC18FXX2
OSC1
I/O (OSC2)
PLL
PIC18FXXX
DS39564B-page 19
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SYSCLK