CY7C4261-10JC Cypress Semiconductor Corp, CY7C4261-10JC Datasheet - Page 2

• Manufacturer Part Number: CY7C4261-10JC
• Description: IC DEEP SYNC FIFO 16KX9 32-PLCC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4261-10JC

• Function: Synchronous
• Memory Size: 144K (16K x 9)
• Data Rate: 100MHz
• Access Time: 8ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1232

Document #: 38-06015 Rev. *B
Functional Description
The CY7C4261/71 provides four status pins: Empty, Full,
Programmable Almost Empty, and Programmable Almost Full.
The Almost Empty/Almost Full flags are programmable to
single word granularity. The programmable flags default to
Empty+7 and Full–7.
The flags are synchronous, i.e., they change state relative to
either the read clock (RCLK) or the write clock (WCLK). When
Pin Definitions
Selection Guide
D
Q
WEN1
WEN2/LD
Dual Mode Pin
REN1, REN2
WCLK
RCLK
EF
FF
PAE
PAF
RS
OE
Maximum Frequency
Maximum Access Time
Minimum Cycle Time
Minimum Data or Enable Set-up
Minimum Data or Enable Hold
Maximum Flag Delay
Active Power Supply
Current (I
Signal Name
0 8
8
CC1
)
Data Inputs
Data Outputs
Write Enable 1
Write Enable 2
Load
Read Enable
Inputs
Write Clock
Read Clock
Empty Flag
Full Flag
Programmable
Almost Empty
Programmable
Almost Full
Reset
Output Enable
Description
Commercial
Industrial/
Military
(continued)
I/O
O Data Outputs for 9-bit bus.
O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
O When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
O When PAE is LOW, the FIFO is almost empty based on the almost empty offset
O When PAF is LOW, the FIFO is almost full based on the almost full offset value
I
I
I
I
I
I
I
I
7C4261/71-10
Data Inputs for 9-bit bus.
The only write enable when device is configured to have programmable flags.
Data is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF
is HIGH. If the FIFO is configured to have two write enables, data is written on a
LOW-to-HIGH transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this
pin operates as a control to write or read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into
the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags,
WEN2/LD is held LOW to write or read the programmable flag offsets.
Enables the device for Read operation. Both REN1 and REN2 must be asserted to
allow a read operation.
The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is HIGH
and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable
flag-offset register.
The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and
the FIFO is not Empty. When WEN2/LD is LOW, RCLK reads data out of the program-
mable flag-offset register.
value programmed into the FIFO. PAE is synchronized to RCLK.
programmed into the FIFO. PAF is synchronized to WCLK.
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If
OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
100
0.5
10
35
40
8
3
8
7C4261/71-15
66.7
10
10
15
35
40
entering or exiting the Empty and Almost Empty states, the
flags are updated exclusively by the RCLK. The flags denoting
Almost Full, and Full states are updated exclusively by WCLK.
The synchronous flag architecture guarantees that the flags
maintain their status for at least one cycle.
All configurations are fabricated using an advanced 0.5
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
4
1
Description
7C4261/71-25
40
15
25
15
35
40
6
1
7C4261/71-35
28.6
20
35
20
35
40
7
2
CY7C4261
CY7C4271
Page 2 of 18
MHz
Unit
mA
ns
ns
ns
ns
ns