EP2S15 ALTERA [Altera Corporation], EP2S15 Datasheet - Page 10

• Manufacturer Part Number: EP2S15
• Description: Stratix II Device Family
• Manufacturer: ALTERA [Altera Corporation]

Functional Description
Figure 2–1. Stratix II Block Diagram
2–2
Stratix II Device Handbook, Volume 1
IOEs
IOEs
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IOEs
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IOEs
LABs
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M512 RAM Blocks for
Dual-Port Memory, Shift
Registers, & FIFO Buffers
IOEs
LABs
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Each Stratix II device I/O pin is fed by an I/O element (IOE) located at
the end of LAB rows and columns around the periphery of the device.
I/O pins support numerous single-ended and differential I/O standards.
Each IOE contains a bidirectional I/O buffer and six registers for
registering input, output, and output-enable signals. When used with
dedicated clocks, these registers provide exceptional performance and
interface support with external memory devices such as DDR and DDR2
SDRAM, RLDRAM II, and QDR II SRAM devices. High-speed serial
interface channels with dynamic phase alignment (DPA) support data
transfer at up to 1 Gbps using LVDS or HyperTransport
standards.
Figure 2–1
DSP
Block
DSP Blocks for
Multiplication and Full
Implementation of FIR Filters
shows an overview of the Stratix II device.
LABs
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IOEs
M4K RAM Blocks
for True Dual-Port
Memory & Other Embedded
Memory Functions
LABs
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IOEs Support DDR, PCI, PCI-X,
SSTL-3, SSTL-2, HSTL-1, HSTL-2,
LVDS, HyperTransport & other
I/O Standards
LABs
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IOEs
M-RAM Block
TM
Altera Corporation
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technology I/O
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May 2007