EP2S15 ALTERA [Altera Corporation], EP2S15 Datasheet - Page 157

• Manufacturer Part Number: EP2S15
• Description: Stratix II Device Family
• Manufacturer: ALTERA [Altera Corporation]

Altera Corporation
May 2007
Preliminary status means the timing model is subject to change. Initially,
timing numbers are created using simulation results, process data, and
other known parameters. These tests are used to make the preliminary
numbers as close to the actual timing parameters as possible.
Final timing numbers are based on actual device operation and testing.
These numbers reflect the actual performance of the device under
worst-case voltage and junction temperature conditions.
I/O Timing Measurement Methodology
Altera characterizes timing delays at the worst-case process, minimum
voltage, and maximum temperature for input register setup time (t
and hold time (t
to calculate t
Figure 5–3
Table 5–33. Stratix II Device Timing Model Status
t
t
SU
H
= – data delay from input pin to input register
EP2S130
EP2S180
= + data delay from input pin to input register
EP2S15
EP2S30
EP2S60
EP2S90
Device
+ micro setup time of the input register
– clock delay from input pin to input register
+ micro hold time of the input register
+ clock delay from input pin to input register
shows the setup and hold timing diagram for input registers.
SU
and t
H
). The Quartus II software uses the following equations
H
timing for Stratix II devices input signals.
Preliminary
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Final
v
v
v
v
v
v
SU
5–21
)