EP2S15 ALTERA [Altera Corporation], EP2S15 Datasheet - Page 233

• Manufacturer Part Number: EP2S15
• Description: Stratix II Device Family
• Manufacturer: ALTERA [Altera Corporation]

Document
Revision History
Altera Corporation
May 2007
May 2007, v4.3
August, 2006,
v4.2
Table 5–103. Document Revision History (Part 1 of 3)
Document
Date and
Version
●
●
●
Moved the Document Revision History section to the
end of the chapter.
●
Updated R
Updated f
Updated f
Updated Table 5–73, Table 5–75, Table 5–77,
Table 5–78, Table 5–79, Table 5–81, Table 5–85,
and Table 5–87.
Table 5–102
devices.
Table 5–103
Note to
(1)
t
t
t
t
t
t
t
t
Symbol
JCP
JCH
JCL
JPSU
JPH
JPCO
JPZX
JPXZ
Table 5–102. Stratix II JTAG Timing Parameters & Values
IN
IN
CONF
(min) in
and f
A 1 ns adder is required for each V
example,
1.8 V.
in
Changes Made
Table
INPFD
Table 5–4
TCK
TCK
TCK
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Table 5–92
shows the JTAG timing parameters and values for Stratix II
shows the revision history for this chapter.
t
5–102:
in
JPCO
clock period
clock high time
clock low time
Table 5–93
= 12 ns if V
Parameter
C C I O
of the TDO I/O bank = 2.5 V, or 13 ns if it equals
C C I O
Stratix II Device Handbook, Volume 1
voltage step down from 3.3 V. For
DC & Switching Characteristics
Summary of Changes
Min
13
13
30
3
5
—
—
—
11
14
14
Max
(1)
(1)
(1)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
5–97