EP2S15 ALTERA [Altera Corporation], EP2S15 Datasheet - Page 159

• Manufacturer Part Number: EP2S15
• Description: Stratix II Device Family
• Manufacturer: ALTERA [Altera Corporation]

Altera Corporation
May 2007
4.
5.
The Quartus II software reports the timing with the conditions shown in
Table 5–34
circuit that is represented by the output timing of the Quartus II software.
Figure 5–4. Output Delay Timing Reporting Setup Modeled by Quartus II
Notes to
(1)
(2)
(3)
Figures 5–5
output enable timing.
Record the time to V
Compare the results of steps 2 and 4. The increase or decrease in
delay should be added to or subtracted from the I/O Standard
Output Adder delays to yield the actual worst-case propagation
delay (clock-to-output) of the PCB trace.
Output pin timing is reported at the output pin of the FPGA device. Additional
delays for loading and board trace delay need to be accounted for with IBIS model
simulations.
V
V
CCPD
CCINT
Output
Buffer
Figure
V
GND
CCIO
is 3.085 V unless otherwise specified.
is 1.12 V unless otherwise specified.
using the above equation.
and
5–4:
Output
5–6
V
show the measurement setup for output disable and
MEAS
MEAS
R
.
S
GND
V
TT
R
C
Stratix II Device Handbook, Volume 1
Figure 5–4
T
L
DC & Switching Characteristics
shows the model of the
Output
Output
p
n
R
D
5–23