EP2S130F1020C3 Altera, EP2S130F1020C3 Datasheet - Page 36

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EP2S130F1020C3

Manufacturer Part Number
EP2S130F1020C3
Description
IC STRATIX II FPGA 130K 1020FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S130F1020C3

Number Of Logic Elements/cells
132540
Number Of Labs/clbs
6627
Total Ram Bits
6747840
Number Of I /o
742
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
132540
# I/os (max)
742
Frequency (max)
778.82MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
132540
Ram Bits
6747840
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2158

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0
TriMatrix Memory
TriMatrix
Memory
2–28
Stratix II Device Handbook, Volume 1
Column IOE
Row IOE
Maximum performance
True dual-port memory
Simple dual-port memory
Single-port memory
Shift register
ROM
FIFO buffer
Pack mode
Byte enable
Address clock enable
Parity bits
Mixed clock mode
Memory initialization (.mif)
Table 2–2. Stratix II Device Routing Scheme (Part 2 of 2)
Table 2–3. TriMatrix Memory Features (Part 1 of 2)
Memory Feature
Source
TriMatrix memory consists of three types of RAM blocks: M512, M4K,
and M-RAM. Although these memory blocks are different, they can all
implement various types of memory with or without parity, including
true dual-port, simple dual-port, and single-port RAM, ROM, and FIFO
buffers.
blocks.
M512 RAM Block
(32 × 18 Bits)
500 MHz
Table 2–3
v
v
v
v
v
v
v
v
v
shows the size and features of the different RAM
v
v v v v
M4K RAM Block
(128 × 36 Bits)
Destination
550 MHz
v v
v
v
v
v
v
v
v
v
v
v
v
v
(4K × 144 Bits)
M-RAM Block
Altera Corporation
420 MHz
v
v
v
v
v
v
v
v
v
(1)
May 2007

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