EP2S130F1020C3 Altera, EP2S130F1020C3 Datasheet - Page 46

• Manufacturer Part Number: EP2S130F1020C3
• Description: IC STRATIX II FPGA 130K 1020FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S130F1020C3

• Number Of Logic Elements/cells: 132540
• Number Of Labs/clbs: 6627
• Total Ram Bits: 6747840
• Number Of I /o: 742
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 132540
• # I/os (max): 742
• Frequency (max): 778.82MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 132540
• Ram Bits: 6747840
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-2158

TriMatrix Memory
Figure 2–26. M-RAM Row Unit Interface to Interconnect
2–38
Stratix II Device Handbook, Volume 1
Direct Link
Interconnects
LAB
Table 2–4
the address and control signal input connections to the row unit interfaces
(L0 to L5 and R0 to R5).
C4 Interconnect
shows the input and output data signal connections along with
M-RAM Block to
LAB Row Interface
Block Interconnect Region
16
Row Interface Block
R4 and R24 Interconnects
Up to 16
Up to 28
M-RAM Block
dataout_a[ ]
datain_a[ ]
addressa[ ]
addr_ena_a
renwe_a
byteena A [ ]
clocken_a
clock_a
aclr_a
Altera Corporation
May 2007