CY7C4261V-15JXC Cypress Semiconductor Corp, CY7C4261V-15JXC Datasheet - Page 21

IC SYNC FIFO MEM 16KX9 32-PLCC

CY7C4261V-15JXC

Manufacturer Part Number
CY7C4261V-15JXC
Description
IC SYNC FIFO MEM 16KX9 32-PLCC
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Datasheet

Specifications of CY7C4261V-15JXC

Access Time
10ns
Memory Size
144K (16K x 9)
Package / Case
32-PLCC
Function
Synchronous
Data Rate
100MHz
Voltage - Supply
3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Number Of Circuits
2
Data Bus Width
9 bit
Bus Direction
Unidirectional
Timing Type
Synchronous
Organization
16 K x 9
Maximum Clock Frequency
66.7 MHz
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Current
25 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C4261V-15JXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Document History Page
Document #: 38-06013 Rev. *F
Document Title: CY7C4261V/CY7C4271V/CY7C4281V/CY7C4291V 16 K / 32 K / 64 K / 128 K × 9 Low-Voltage Deep Sync™ FIFOs
Document Number: 38-06013
REV.
*C
*D
*A
*B
*E
*F
**
ECN NO.
2896378
2906525
3069396
3210221
106474
127858
386127
Issue Date
03/19/2010
04/07/2010
10/22/2010
03/25/2011
See ECN
09/15/01
09/04/03
Change
Orig. of
RAME
RAME
ADMU
ADMU
FSG
ESH
SZV
Changed Spec number from 38-00656 to 38-06013
Changed: t
Fixed flag timing diagram in Switching Waveforms section
Added Pb-Free logo to top of front page
Added CY7C4291V-15JXC, CY7C91V-10JXC, CY7C4281V-10JXC,
CY7C4271V-10JXC, CY7C4261V-10JXC, CY7C4261V-15JXC to ordering infor-
mation.
Removed inactive parts from Ordering information and updated package diagram.
Removed inactive part from Ordering Information table.
Corrected data in Programmable Flag (PAE, PAF) Operation:
a) PAF is synchronized to the LOW-to-HIGH transition of RCLK by one flip-flop and
is LOW when the FIFO contains n or fewer unread words. Changed PAF to PAE.
b) PAE is synchronized to the LOW-to-HIGH transition of WCLK by one flip-flop and
is set LOW when the number of unread words in the FIFO is greater than or equal
to CY7C4261 (16K-m) and CY7C4271 (32K-m). Changed PAE to PAF.
Added Acronyms,
Removed CY7C4271V-10JC part from Ordering Information table.
SKEW2
to t
Document
SKEW1
in Switching Waveforms “Empty Flag Timing” diagram
Description of Change
Conventions, and
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
Ordering Code
Definition.
Page 21 of 22
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