CY7C4261V-15JXC Cypress Semiconductor Corp, CY7C4261V-15JXC Datasheet - Page 5

• Manufacturer Part Number: CY7C4261V-15JXC
• Description: IC SYNC FIFO MEM 16KX9 32-PLCC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4261V-15JXC

• Access Time: 10ns
• Memory Size: 144K (16K x 9)
• Package / Case: 32-PLCC
• Function: Synchronous
• Data Rate: 100MHz
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Circuits: 2
• Data Bus Width: 9 bit
• Bus Direction: Unidirectional
• Timing Type: Synchronous
• Organization: 16 K x 9
• Maximum Clock Frequency: 66.7 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 25 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Architecture
The CY7C4261/71/81/91V consists of an array of 16 K, 32 K,
64 K, or 128 K words of nine bits each (implemented by a
dual-port array of SRAM cells), a read pointer, a write pointer,
control signals (RCLK, WCLK, REN1, REN2, WEN1, WEN2,
RS), and flags (EF, PAE, PAF, FF).
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS) cycle.
This causes the FIFO to enter the Empty condition signified by
EF being LOW. All data outputs (Q
rising edge of RS. In order for the FIFO to reset to its default
state, the user must not read or write while RS is LOW. All flags
are guaranteed to be valid t
FIFO Operation
When the WEN1 signal is active LOW, WEN2 is active HIGH,
and FF is active HIGH, data present on the D
into the FIFO on each rising edge of the WCLK signal. Similarly,
when the REN1 and REN2 signals are active LOW and EF is
active HIGH, data in the FIFO memory will be presented on the
Q
RCLK while REN1 and REN2 are active. REN1 and REN2 must
set up t
and WEN2 must occur t
function.
An output enable (OE) pin is provided to three-state the Q
outputs when OE is asserted. When OE is enabled (LOW), data
in the output register will be available to the Q
t
data on the FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional writes
when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q
after additional reads occur.
Write Enable 1 (WEN1). If the FIFO is configured for
programmable flags, Write Enable 1 (WEN1) is the only write
enable control pin. In this configuration, when Write Enable 1
(WEN1) is LOW, data can be loaded into the input register and
RAM array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored is the RAM array sequentially and
independently of any on-going read operation.
Write Enable 2/Load (WEN2/LD). This is a dual-purpose pin.
The FIFO is configured at Reset to have programmable flags or
to have two write enables, which allows for depth expansion. If
Write Enable 2/Load (WEN2/LD) is set active HIGH at Reset (RS
= LOW), this pin operates as a second write enable pin.
If the FIFO is configured to have two write enables, when Write
Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/LD) is
HIGH, data can be loaded into the input register and RAM array
on the LOW-to-HIGH transition of every write clock (WCLK).
Data is stored in the RAM array sequentially and independently
of any on-going read operation.
Document #: 38-06013 Rev. *F
OE
0-8
. If devices are cascaded, the OE function will only output
outputs. New data will be presented on each rising edge of
ENS
before RCLK for it to be a valid read function. WEN1
ENS
before WCLK for it to be a valid write
RSF
after RS is taken LOW.
0–8
) go LOW t
0 –8
0-8
0-8
RSF
pins is written
outputs after
outputs even
after the
0–8
Programming
When WEN2/LD is held LOW during Reset, this pin is the load
(LD) enable for flag offset programming. In this configuration,
WEN2/LD can be used to access the four 9-bit offset registers
contained in the CY7C4261/71/81/91V for writing or reading data
to these registers.
When the device is configured for programmable flags and both
WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH transition
of WCLK writes data from the data inputs to the empty offset least
significant bit (LSB) register. The second, third, and fourth
LOW-to-HIGH transitions of WCLK store data in the empty offset
most significant bit (MSB) register, full offset LSB register, and
full offset MSB register, respectively, when WEN2/LD and WEN1
are LOW. The fifth LOW-to-HIGH transition of WCLK while
WEN2/LD and WEN1 are LOW writes data to the empty LSB
register again.
values for the various device types.
Figure 1. Offset Register Location and Default Values
8
8
8
8
8
8
8
8
7
7
7
7
7
7
Empty Offset (LSB) Reg.
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
Empty Offset (LSB) Reg.
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
Default Value = 000h
Default Value = 000h
16 k
64k x 9
5
5
Default Value = 000h
Default Value = 000h
x 9
Figure 1
(MSB)
(MSB)
(MSB)
(MSB)
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
shows the registers sizes and default
0
0
0
0
0
0
0
0
8
8
8
8
8
8
8
8
7
7
7
7
Empty Offset (LSB) Reg.
Default Value = 007h
6
Full Offset (LSB) Reg
Default Value = 007h
Default Value = 000h
Default Value = 000h
Empty Offset (LSB) Reg.
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
6
32 k x 9
128k x 9
Default Value = 000h
Default Value = 000h
(MSB)
(MSB)
Page 5 of 22
(MSB)
(MSB)
0
0
0
0
0
0
0
0
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