CY7C4261V-15JXC Cypress Semiconductor Corp, CY7C4261V-15JXC Datasheet - Page 4

• Manufacturer Part Number: CY7C4261V-15JXC
• Description: IC SYNC FIFO MEM 16KX9 32-PLCC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4261V-15JXC

• Access Time: 10ns
• Memory Size: 144K (16K x 9)
• Package / Case: 32-PLCC
• Function: Synchronous
• Data Rate: 100MHz
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Circuits: 2
• Data Bus Width: 9 bit
• Bus Direction: Unidirectional
• Timing Type: Synchronous
• Organization: 16 K x 9
• Maximum Clock Frequency: 66.7 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 25 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Pin Definitions
Document #: 38-06013 Rev. *F
Pin Configuration
1–6, 30–32 D
1–6, 30–32 Q
28
26
10, 12
27
11
14
15
8
7
29
13
Pin No.
WEN1
WEN2/LD
Dual mode pin
REN1, REN2
WCLK
RCLK
EF
FF
PAE
PAF
RS
OE
Signal Name
08
08
Data inputs
Data outputs
Write Enable 1
Write Enable 2
Load
Read Enable 
inputs
Write Clock
Read Clock
Empty Flag
Full Flag
Programmable
Almost Empty
Programmable
Almost Full
Reset
Output Enable
Description
I/O
REN1
RCLK
REN2
O Data outputs for 9-bit bus.
O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
O When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
O When PAE is LOW, the FIFO is almost empty based on the almost empty offset
O When PAF is LOW, the FIFO is almost full based on the almost full offset value
GND
I
I
I
I
I
I
I
I
PAE
PAF
OE
D
D
1
0
Data inputs for 9-bit bus.
The only write enable when device is configured to have programmable flags.
Data is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted
and FF is HIGH. If the FIFO is configured to have two write enables, data is
written on a LOW-to-HIGH transition of WCLK when WEN1 is LOW and
WEN2/LD and FF are HIGH.
If HIGH at reset, this pin operates as a second write enable. If LOW at reset,
this pin operates as a control to write or read the programmable flag offsets.
WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data
will not be written into the FIFO if the FF is LOW. If the FIFO is configured to
have programmable flags, WEN2/LD is held LOW to write or read the
programmable flag offsets.
Enables the device for Read operation. Both REN1 and REN2 must be asserted
to allow a read operation.
The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD
is HIGH and the FIFO is not full. When LD is asserted, WCLK writes data into
the programmable flag-offset register.
The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW
and the FIFO are not Empty. When WEN2/LD is LOW, RCLK reads data out of
the programmable flag-offset register.
value programmed into the FIFO. PAE is synchronized to RCLK.
programmed into the FIFO. PAF is synchronized to WCLK.
Resets device to empty condition. A reset is required before an initial read or
write operation after power-up.
When OE is LOW, the FIFO’s data outputs drive the bus to which they are
connected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance)
state.
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20
4 3 2 1
CY7C4261V
CY7C4271V
CY7C4281V
CY7C4291V
Top View
PLCC
32
31 30
29
28
27
26
25
24
23
22
21
RS
WEN1
WCLK
WEN2/LD
V
Q
Q
Q
Q
CC
8
7
6
5
Description
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
Page 4 of 22
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