MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 229
MC68030FE25C
Manufacturer Part Number
MC68030FE25C
Description
IC MPU 32BIT ENHANCED 132-CQFP
Manufacturer
Freescale Semiconductor
Specifications of MC68030FE25C
Processor Type
M680x0 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-CQFP
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
CQUAD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68030FE25C
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68030FE25C
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
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7
7.4 CPU SPACE CYCLES
7-68
A3/A2=00 (i.e., the count sequence wraps back to zero and continues as
to A3/A2 = 00.
State 8
State 9
for the duration of a burst transfer operation (including the first transfer before
word transferred is not located at A3/A2= 00), the external hardware must
correctly control the continuation or termination of the burst transfer as
of the most significant long word of the 16-byte image (A3/A2= 11) or may
4-1. The area selected by FC0-FC2=$7 is classified as the CPU space. The
State 7
Note that the address bus of the MC68030 remains driven to a constant value
burst mode is entered). If an external memory system requires incrementing
of the long-word base address to supply successive long words of infor-
mation, this function must be performed by external hardware. Additionally,
in the case of burst transfers that cross a 16-byte boundary (i.e., the first long
desired. The burst may be terminated by negating CBACK during the transfer
be continued (with CBACK asserted) by providing the long word located at
necessary). The MC68030 caches assume the higher order address lines
(A4-A31) remain unchanged as the long-word accesses wrap back around
FC0-FC2 select user and supervisor program and data areas as listed in Table
interrupt acknowledge, breakpoint acknowledge, and coprocessor commu-
nication cycles described in the following sections utilize CPU space.
the processor cannot continue to accept more data after this. The data
The processor negates AS, DS, and DBEN during S9. It holds the address,
for data described for $3 apply here.
scribed for S3 apply here.
This state is identical to $4 except that CBREQ is negated, indicating that
During this state, the processor negates CBREQ, and the memory device
may negate CBACK. Aside from this, all other bus signals driven by the
processor remain driven. The same hold times for STERM and data de-
latched at the end of $8 corresponds to the fourth long word of the burst.
R/W,
SIZ0-SIZ1, and FC0-FC2 valid throughout $9. The same hold times
MC68030 USER'S MANUAL
MOTOROLA
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