MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 408

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
ORDER
SAVE
the state frame in memory, and this word is the first word transferred for
format word does not contain information relevant to the coprocessor state
frame, but serves to keep the information in the state frame a multiple of
for that coprocessor. This description of a coprocessor context includes the
The processor stores the coprocessor format word at the lowest address of
four bytes in size. The number of entries following the format word (at higher
addresses) is determined.
The information in a coprocessor state frame describes a context of operation
program invisible state information and, optionally, the program visible state
information. The program invisible state information consists of any internal
is necessary for the coprocessor to continue its operation at the point of
suspension. Program visible state information includes the contents of all
be directly accessed using the coprocessor instruction set. The information
saved by the cpSAVE instruction must include the program invisible state
state of the coprocessor, the cpSAVE and cpRESTORE instructions should
only transfer the program invisible state information to minimize interrupt
both the cpSAVE and the cpRESTORE instructions. The word following the
registers or status information that cannot be accessed by the program but
registers that appear in the coprocessor programming model and that can
information. If cpGEN instructions are provided to save the program visible
latency during a save or restore operation.
n-]
n-2
n
0
RESTORE
ORDER
0
2
3
1
Figure 10-14. Coprocessor State Frame Format in Memory
31
FORMAT
MC68030 USER'S MANUAL
1
23
COPROCESSOR.DEPENDENT INFORMATION
LENGTH
1
15
(UNUSED, RESERVED)
10-21
0
10